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Freescale Semiconductor
Technical Data
Document Number: MPC8640DEC Rev. 1, 11/2008
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications
1 Overview
Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . .5 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .13 Input Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .17 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . .18 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Ethernet Management Interface Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . .59 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Signal Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 System Design Information . . . . . . . . . . . . . . . . . . . .121 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . .131 Document Revision History. . . . . . . . . . . . . . . . . . . .135
The MPC8640 processor family integrates either one or two Power ArchitectureTM e600 processor cores with system logic required for networking, storage, wireless infrastructure, and general-purpose embedded applications. The MPC8640 integrates one e600 core while the MPC8640D integrates two cores. This section provides a high-level overview of the MPC8640 and MPC8640D features. When referring to the MPC8640 throughout the document, the functionality described applies to both the MPC8640 and the MPC8640D. Any differences specific to the MPC8640D are noted. Figure 1 shows the major functional units within the MPC8640 and MPC8640D. The major difference between the MPC8640 and MPC8640D is that there are two cores on the MPC8640D.
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22.
(c) Freescale Semiconductor, Inc., 2008. All rights reserved.
Overview
e600 Core Block
e600 Core
32-Kbyte L1 Instruction Cache 32-Kbyte L1 Data Cache 1-Mbyte L2 Cache
e600 Core Block
e600 Core
32-Kbyte L1 Instruction Cache 32-Kbyte L1 Data Cache 1-Mbyte L2 Cache
MPX Bus MPX Coherency Module (MCM) Platform Bus
SDRAM SDRAM ROM, GPIO
DDR SDRAM Controller DDR SDRAM Controller Local Bus Controller (LBC) Multiprocessor Programmable Interrupt Controller (MPIC) Dual Universal Asynchronous Receiver/Transmitter (DUART) I2C Controller I2C Controller Enhanced TSEC Controller 10/100/1Gb Enhanced TSEC Controller 10/100/1Gb PCI Express Interface OCeaN Switch Fabric Serial RapidIO Interface or PCI Express Interface
Platform
IRQs
Serial
I2C I2C RMII, GMII, MII, RGMII, TBI, RTBI
[ x1/x2/x4/x8 PCI Exp (4 GB/s) AND 1x/4x SRIO (2.5 GB/s) ] OR [2-x1/x2/x4/x8 PCI Express (8 GB/S) ]
RMII, GMII, MII, RGMII, TBI, RTBI
RMII, GMII, MII, RGMII, TBI, RTBI
Enhanced TSEC Controller 10/100/1Gb Four-Channel DMA Controller External Control
RMII, GMII, MII, RGMII, TBI, RTBI
Enhanced TSEC Controller 10/100/1Gb
Figure 1. MPC8640 and MPC8640D
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 2 Freescale Semiconductor
Overview
1.1
Key Features
The following lists an overview of the MPC8640 key feature set: * Major features of the e600 core are as follows: -- High-performance, 32-bit superscalar microprocessor that implements the PowerPC ISA -- Eleven independent execution units and three register files - Branch processing unit (BPU) - Four integer units (IUs) that share 32 GPRs for integer operands - 64-bit floating-point unit (FPU) - Four vector units and a 32-entry vector register file (VRs) - Three-stage load/store unit (LSU) -- Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions, respectively, in a cycle. -- Rename buffers -- Dispatch unit -- Completion unit -- Two separate 32-Kbyte instruction and data level 1 (L1) caches -- Integrated 1-Mbyte, eight-way set-associative unified instruction and data level 2 (L2) cache with ECC -- 36-bit real addressing -- Separate memory management units (MMUs) for instructions and data -- Multiprocessing support features -- Power and thermal management -- Performance monitor -- In-system testability and debugging features -- Reliability and serviceability * MPX coherency module (MCM) -- Ten local address windows plus two default windows -- Optional low memory offset mode for core 1 to allow for address disambiguation * Address translation and mapping units (ATMUs) -- Eight local access windows define mapping within local 36-bit address space -- Inbound and outbound ATMUs map to larger external address spaces -- Three inbound windows plus a configuration window on PCI Express -- Four inbound windows plus a default window on serial RapidIO -- Four outbound windows plus default translation for PCI Express -- Eight outbound windows plus default translation for serial RapidIO with segmentation and sub-segmentation support
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 3
Overview
*
*
*
*
DDR memory controllers -- Dual 64-bit memory controllers (72-bit with ECC) -- Support of up to a 266 MHz clock rate and a 533 MHz DDR2 SDRAM -- Support for DDR, DDR2 SDRAM -- Up to 16 Gbytes per memory controller -- Cache line and page interleaving between memory controllers. Serial RapidIO interface unit -- Supports RapidIO Interconnect Specification, Revision 1.2 -- Both 1x and 4x LP-Serial link interfaces -- Transmission rates of 1.25-, 2.5-, and 3.125-Gbaud (data rates of 1.0-, 2.0-, and 2.5-Gbps) per lane -- RapidIO-compliant message unit -- RapidIO atomic transactions to the memory controller PCI Express interface -- PCI Express 1.0a compatible -- Supports x1, x2, x4, and x8 link widths -- 2.5 Gbaud, 2.0 Gbps lane Four enhanced three-speed Ethernet controllers (eTSECs) -- Three-speed support (10/100/1000 Mbps) -- Four IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers -- Support of the following physical interfaces: MII, RMII, GMII, RGMII, TBI, and RTBI -- -- -- -- -- -- -- Support a full-duplex FIFO mode for high-efficiency ASIC connectivity TCP/IP off-load Header parsing Quality of service support VLAN insertion and deletion MAC address recognition Buffer descriptors are backward compatible with PowerQUICC II and PowerQUICC III programming models -- RMON statistics support -- MII management interface for control and status Programmable interrupt controller (PIC) -- Programming model is compliant with the OpenPIC architecture -- Supports 16 programmable interrupt and processor task priority levels -- Supports 12 discrete external interrupts and 48 internal interrupts -- Eight global high resolution timers/counters that can generate interrupts -- Allows processors to interrupt each other with 32b messages
*
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 4 Freescale Semiconductor
Electrical Characteristics
*
*
*
*
*
*
* *
-- Support for PCI-Express message-shared interrupts (MSIs) Local bus controller (LBC) -- Multiplexed 32-bit address and data operating at up to 125 MHz -- Eight chip selects support eight external slaves Integrated DMA controller -- Four-channel controller -- All channels accessible by both the local and the remote masters -- Supports transfers to or from any local memory or I/O port -- Ability to start and flow control each DMA channel from external 3-pin interface Device performance monitor -- Supports eight 32-bit counters that count the occurrence of selected events -- Ability to count up to 512 counter-specific events -- Supports 64 reference events that can be counted on any of the 8 counters -- Supports duration and quantity threshold counting -- Burstiness feature that permits counting of burst events with a programmable time between bursts -- Triggering and chaining capability -- Ability to generate an interrupt on overflow Dual I2C controllers -- Two-wire interface -- Multiple master support -- Master or slave I2C mode support -- On-chip digital filtering rejects spikes on the bus Boot sequencer -- Optionally loads configuration data from serial ROM at reset via the I2C interface -- Can be used to initialize configuration registers and/or memory -- Supports extended I2C addressing mode -- Data integrity checked with preamble signature and CRC DUART -- Two 4-wire interfaces (SIN, SOUT, RTS, CTS) -- Programming model compatible with the original 16450 UART and the PC16550D IEEE 1149.1-compliant, JTAG boundary scan Available as 1023 pin Hi-CTE flip chip ceramic ball grid array (FC-CBGA)
2
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8640. The MPC8640 is currently targeted to these specifications.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 5
Electrical Characteristics
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings1
Characteristic Symbol VDD_Core0, VDD_Core1 AVDD_Core0, AVDD_Core1 SVDD XVDD_SRDS1 XVDD_SRDS2 AV DD_SRDS1, AVDD_SRDS2 VDD_PLAT AVDD_LB, AVDD_PLAT D1_GVDD, D2_GVDD LVDD TVDD OVDD Absolute Maximum Value -0.3 to 1.21 V -0.3 to 1.21 V -0.3 to 1.21 V -0.3 to 1.21V -0.3 to 1.21 V -0.3 to 1.21V -0.3 to 1.21V -0.3 to 1.21V -0.3 to 2.75 V -0.3 to 1.98 V -0.3 to 3.63 V -0.3 to 2.75 V Unit Notes V V V V V V V V V V V V V V V 3 3 4 4 4 4 2
Table 1 provides the absolute maximum ratings.
Cores supply voltages Cores PLL supply SerDes Transceiver Supply (Ports 1 and 2) SerDes Serial I/O Supply Port 1 SerDes Serial I/O Supply Port 2 SerDes DLL and PLL supply voltage for Port 1 and Port 2 Platform Supply voltage Local Bus and Platform PLL supply voltage DDR and DDR2 SDRAM I/O supply voltages
eTSEC 1 and 2 I/O supply voltage
eTSEC 3 and 4 I/O supply voltage
-0.3 to 3.63 V -0.3 to 2.75 V
Local Bus, DUART, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, I2C, JTAG and Miscellaneous I/O voltage Input voltage DDR and DDR2 SDRAM signals DDR and DDR2 SDRAM reference Three-speed Ethernet signals DUART, Local Bus, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, I2C, JTAG and Miscellaneous I/O voltage
-0.3 to 3.63V
Dn_MVIN Dn_MVREF LVIN TVIN OV IN
- 0.3 to (Dn_GVDD + 0.3) - 0.3 to (Dn_GVDD/2 + 0.3) GND to (LVDD+ 0.3) GND to (TVDD+ 0.3) GND to (OVDD+ 0.3)
V V V V
5
5 5
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 6 Freescale Semiconductor
Electrical Characteristics
Table 1. Absolute Maximum Ratings1 (continued)
Characteristic Storage temperature range Symbol TSTG Absolute Maximum Value -55 to 150 Unit Notes C
Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Core 1 characteristics apply only to MPC8640D. If two separate power supplies are used for V DD_Core0 and VDD_Core1, they must be kept within 100 mV of each other during normal run time. 3. The -0.3 to 2.75 V range is for DDR and -0.3 to 1.98 V range is for DDR2. 4. The 3.63V maximum is only supported when the port is configured in GMII, MII, RMII, or TBI modes; otherwise the 2.75V maximum applies. See Section 8.2, "FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications" for details on the recommended operating conditions per protocol. 5. During run time (M,L,T,O)VIN and Dn_MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
2.1.2
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8640. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. For details on order information and specific operating conditions for parts, see Section 21, "Ordering Information."
Table 2. Recommended Operating Conditions
Characteristic Cores supply voltages Symbol VDD_Core0, VDD_Core1 AVDD_Core0, AV DD_Core1 SVDD XVDD_SRDS1 XVDD_SRDS2 AVDD_SRDS1, AVDD_SRDS2 VDD_PLAT AVDD_LB, AVDD_PLAT D1_GV DD, D2_GVDD LVDD Recommended Value 1.05 50 mV 0.95 50 mV 1.05 50 mV 0.95 50 mV 1.05 50 mV 1.05 50 mV 1.05 50 mV 1.05 50 mV 1.05 50 mV 1.05 50 mV 2.5 V 125 mV 1.8 V 90 mV 3.3 V 165 mV 2.5 V 125 mV V V V V V V V V V 7 7 8 8 V Unit V Notes 1, 2 1, 2, 10 11 10, 11 9
Cores PLL supply
SerDes Transceiver Supply (Ports 1 and 2) SerDes Serial I/O Supply Port 1 SerDes Serial I/O Supply Port 2 SerDes DLL and PLL supply voltage for Port 1 and Port 2 Platform Supply voltage Local Bus and Platform PLL supply voltage DDR and DDR2 SDRAM I/O supply voltages
eTSEC 1 and 2 I/O supply voltage
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 7
Electrical Characteristics
Table 2. Recommended Operating Conditions (continued)
Characteristic eTSEC 3 and 4 I/O supply voltage Symbol TVDD OV DD Recommended Value 3.3 V 165 mV 2.5 V 125 mV Local Bus, DUART, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, I2C, JTAG and Miscellaneous I/O voltage Input voltage DDR and DDR2 SDRAM signals DDR and DDR2 SDRAM reference Three-speed Ethernet signals DUART, Local Bus, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, I2C, JTAG and Miscellaneous I/O voltage Junction temperature range 3.3 V 165 mV Unit V V V Notes 8 8 5
Dn_MV IN Dn_MV REF LVIN TVIN OVIN
GND to Dn_GVDD Dn_GVDD/2 1% GND to LVDD GND to TVDD GND to OVDD
V V V V
3, 6
4, 6 5,6
TJ
0 to 105 -40 to 105
C 12
Notes: 1. Core 1 characteristics apply only to MPC8640D 2. If two separate power supplies are used for VDD_Core0 and VDD_Core1, they must be at the same nominal voltage and the individual power supplies must be tracked and kept within 100 mV of each other during normal run time. 3. Caution: Dn_MVIN must meet the overshoot/undershoot requirements for Dn_GVDD as shown in Figure 2. 4. Caution: L/TVIN must meet the overshoot/undershoot requirements for L/TVDD as shown in Figure 2 during regular run time. 5. Caution: OVIN must meet the overshoot/undershoot requirements for OVDD as shown in Figure 2 during regular run time. 6. Timing limitations for M,L,T,O)VIN and Dn_MVREF during regular run time is provided in Figure 2 7. The 2.5 V 125 mV range is for DDR and 1.8 V 90 mV range is for DDR2. 8. See Section 8.2, "FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications" for details on the recommended operating conditions per protocol. 9. The PCI Express interface of the device is expected to receive signals from 0.175 to 1.2 V. For more information refer to Section 14.4.3, "Differential Receiver (RX) Input Specifications." 10. Applies to Part Number MC8640wxx1067NC only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V devices. Refer to Table 73 Part Numbering Nomenclature to determine if the device has been marked for VDD_Coren = 0.95 V. 11. This voltage is the input to the filter discussed in Section 20.2, "Power Supply Design and Sequencing" and not necessarily the voltage at the AV DD_Coren pin, which may be reduced from VDD_Coren by the filter. 12. Applies to part number MC8640DTxxyyyyaC. Refer to Table 73 Part Numbering Nomenclature to determine if the device has been marked for extended operating temperature range.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 8 Freescale Semiconductor
Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8640.
L/T/Dn_G/O/X/SV DD + 20% L/T/Dn_G/O/X/SVDD + 5% VIH L/T/Dn_G/O/X/SVDD
GND GND - 0.3 V VIL GND - 0.7 V Not to Exceed 10% of tCLK1
Note: 1. tCLK references clocks for various functional blocks as follows:
DDRn = 10% of Dn_MCK period eTsecn = 10% of ECn_GTX_CLK125 period Local Bus = 10% of LCLK[0:2] period I2C = 10% of SYSCLK JTAG = 10% of SYSCLK Figure 2. Overshoot/Undershoot Voltage for Dn_M/O/L/TVIN
The MPC8640 core voltage must always be provided at nominal VDD_Coren (See Table 2 for actual recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and L/TVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced to each externally supplied Dn_MVREF signal (nominally set to Dn_GVDD/2) as is appropriate for the (SSTL-18 and SSTL-25) electrical signaling standards.
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 9
Electrical Characteristics
Table 3. Output Drive Capability
Driver Type DDR1 signal DDR2 signal Local Bus signals eTSEC/10/100 signals Programmable Output Impedance () 18 36 (half strength mode) 18 36 (half strength mode) 45 25 45 30 DUART, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, JTAG and Miscellaneous I/O voltage I2C SRIO, PCI Express 45 Supply Voltage Dn_GVDD = 2.5 V Dn_GVDD = 1.8 V OVDD = 3.3 V T/LVDD = 3.3 V T/LVDD = 2.5 V OVDD = 3.3 V Notes 4, 9 1, 5, 9 2, 6 6 6 6
150 100
OVDD = 3.3 V SVDD = 1.1/1.05 V
7 3, 8
Notes: 1. See the DDR Control Driver registers in the MPC8641D reference manual for more information. 2. Only the following local bus signals have programmable drive strengths: LALE, LAD[0:31], LDP[0:3], LA[27:31], LCKE, LCS[1:2], LWE[0:3], LGPL1, LGPL2, LGPL3, LGPL4, LGPL5, LCLK[0:2]. The other local bus signals have a fixed drive strength of 45 ohms. See the POR Impedance Control register in the MPC8641D reference manual for more information about local bus signals and their drive strength programmability. 3. See Section 17, "Signal Listings" for details on resistor requirements for the calibration of SDn_IMP_CAL_TX and SDn_IMP_CAL_RX transmit and receive signals. 4. Stub Series Terminated Logic (SSTL-25) type pins. 5. Stub Series Terminated Logic (SSTL-18) type pins. 6. Low Voltage Transistor-Transistor Logic (LVTTL) type pins. 7. Open Drain type pins. 8. Low Voltage Differential Signaling (LVDS) type pins. 9. The drive strength of the DDR interface in half strength mode is at Tj = 105C and at Dn_GV DD (min).
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 10 Freescale Semiconductor
Electrical Characteristics
2.2
Power Up/Down Sequence
The MPC8640 requires its power rails to be applied in a specific sequence in order to ensure proper device operation.
NOTE
The recommended maximum ramp up time for power supplies is 20 milliseconds. The chronological order of power up is: 1. All power rails other than DDR I/O (Dn_GVDD, and Dn_MVREF).
NOTE
There is no required order sequence between the individual rails for this item (# 1). However, VDD_PLAT, AVDD_PLAT rails must reach 90% of their recommended value before the rail for Dn_GVDD, and Dn_MVREF (in next step) reaches 10% of their recommended value. AVDD type supplies must be delayed with respect to their source supplies by the RC time constant of the PLL filter circuit described in Section 20.2.1, "PLL Power Supply Filtering". 2. Dn_GVDD, Dn_MVREF
NOTE
It is possible to leave the related power supply (Dn_GVDD, Dn_MVREF) turned off at reset for a DDR port that will not be used. Note that these power supplies can only be powered up again at reset for functionality to occur on the DDR port. 3. SYSCLK The recommended order of power down is as follows: 1. Dn_GVDD, Dn_MVREF 2. All power rails other than DDR I/O (Dn_GVDD, Dn_MVREF).
NOTE
SYSCLK may be powered down simultaneous to either of item # 1 or # 2 in the power down sequence. Beyond this, the power supplies may power down simultaneously if the preservation of DDRn memory is not a concern. See Figure 3 for more details on the Power and Reset Sequencing details
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 11
Electrical Characteristics
Figure 3 illustrates the Power Up sequence as described above.
3.3 V
If 1 L/TVDD=2.5 V
L/T/OVDD
DC Power Supply Voltage
2.5 V Dn_GVDD, = 1.8/2.5 V Dn_MVREF VDD_PLAT, AVDD_PLAT AVDD_LB, SVDD, XVDD_SRDSn AVDD_SRDSn VDD_Coren, AVDD_Coren
7
1.8 V
1.2 V
100 s Platform PLL Relock Time 3
0 Power Supply Ramp Up 2 SYSCLK 8 (not drawn to scale)
9
Time
HRESET (& TRST) Asserted for 100 s after SYSCLK is functional 4
e6005 PLL
Reset Configuration Pins Cycles Setup and hold Time 6 Notes: 1. Dotted waveforms correspond to optional supply values for a specified power supply. See Table 2. 2. The recommended maximum ramp up time for power supplies is 20 milliseconds. 3. Refer to Section 5, "RESET Initialization" for additional information on PLL relock and reset signal assertion timing requirements. 4. Refer to Table 10 for additional information on reset configuration pin setup timing requirements. In addition see Figure 68 regarding HRESET and JTAG connection details including TRST. 5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles. 6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration inputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cycles after HRESET has negated (hold requirement). See Section 5, "RESET Initialization" for more information on setup and hold time of reset configuration signals. 7. VDD_PLAT, AVDD_PLAT must strictly reach 90% of their recommended voltage before the rail for Dn_GVDD, and Dn_MVREF reaches 10% of their recommended voltage. 8. SYSCLK must be driven only AFTER the power for the various power supplies is stable. 9. In device sleep mode, the reset configuration signals for DRAM types (TSEC2_TXD[4],TSEC2_TX_ER) must be valid BEFORE HRESET is asserted.
Figure 3. MPC8640 Power-Up and Reset Sequence
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 12 Freescale Semiconductor
Power Characteristics
3
Power Characteristics
Table 4. MPC8640D Power Dissipation (Dual Core)
Power Mode Typical Thermal Maximum Typical Thermal Maximum Typical Thermal Maximum 1067 MHz 533 MHz 0.95/1.05 V 1000 MHz 500 MHz 1.05 V 1250 MHz 500 MHz 1.05 V Core Frequency (MHz) Platform Frequency (MHz) VDD_Coren, VDD_PLAT (Volts) Junction Temperature 65 oC 105 oC 65 oC 105 oC 65 oC 105 oC Power (Watts) 21.7 27.3 31 18.9 23.8 27 15.7 19.5 22 Notes 1, 2 1, 3 1, 4 1, 2 1, 3 1, 4 1, 2, 5 1, 3, 5 1, 4, 5
The power dissipation for the dual core MPC8640D device is shown in Table 4.
Notes: 1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations. The values do not include power dissipation for I/O supplies. 2. Typical power is an average value measured at the nominal recommended core voltage (VDD_Coren) and 65C junction temperature (see Table 2)while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz with one core at 100% efficiency and the second core at 65% efficiency. 3. Thermal power is the average power measured at nominal core voltage (VDD_Coren) and maximum operating junction temperature (see Table 2) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz on both cores and a typical workload on platform interfaces. 4. Maximum power is the maximum power measured at nominal core voltage (VDD_Coren) and maximum operating junction temperature (see Table 2) while running a test which includes an entirely L1-cache-resident, contrived sequence of instructions which keep all the execution units maximally busy on both cores. 5. These power numbers are for Part Number MC8640Dwxx1067NC and MC8640wxx1067NC only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 13
Input Clocks
The power dissipation for the MPC8640 single core device is shown in Table 5.
Table 5. MPC8640 Power Dissipation (Single Core)
Power Mode Typical Thermal Maximum Typical Thermal Maximum Typical Thermal Maximum Notes: 1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations. The values do not include power dissipation for I/O supplies. 2. Typical power is an average value measured at the nominal recommended core voltage (VDD_Coren) and 65C junction temperature (see Table 2)while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz. 3. Thermal power is the average power measured at nominal core voltage (VDD_Coren) and maximum operating junction temperature (see Table 2) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz and a typical workload on platform interfaces. 4. Maximum power is the maximum power measured at nominal core voltage (VDD_Coren) and maximum operating junction temperature (see Table 2) while running a test which includes an entirely L1-cache-resident, contrived sequence of instructions which keep all the execution units maximally busy. 5. These power numbers are for Part Number MC8640Dwxx1067NC and MC8640wxx1067NC only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V. 1067 MHz 533 MHz 0.95 V, 1.05 V 1000 MHz 500 MHz 1.05 V 1250 MHz 500 MHz 1.05 V Core Frequency (MHz) Platform Frequency (MHz) VDD_Coren, VDD_PLAT (Volts) Junction Temperature 65 oC 105 oC 65 C 105 oC 65
oC o
Power (Watts) 13.3 16.5 19 11.9 14.8 17 10.1 12.3
Notes 1, 2 1, 3 1, 4 1, 2 1, 3 1, 4 1, 2, 5 1, 3, 5 1, 4, 5
105 oC
14
4
Input Clocks
Table 6. SYSCLK DC Electrical Characteristics (OVDD = 3.3 V 165 mV.)
Parameter High-level input voltage Low-level input voltage Input current (VIN 1 = 0 V or VIN = V DD) Symbol VIH VIL IIN Min 2 -0.3 -- Max OVDD + 0.3 0.8 5 Unit V V A
Table 6 provides the system clock (SYSCLK) DC specifications for the MPC8640.
Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 14 Freescale Semiconductor
Input Clocks
4.1
System Clock Timing
Table 7. SYSCLK AC Timing Specifications
Table 7 provides the system clock (SYSCLK) AC timing specifications for the MPC8640.
At recommended operating conditions (see Table 2) with OVDD = 3.3 V 165 mV. Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle SYSCLK jitter Symbol fSYSCLK tSYSCLK tKH, tKL tKHK/tSYSCLK -- Min 66 6 0.6 40 -- Typical -- -- 1.0 -- -- Max 166.66 -- 1.2 60 150 Unit MHz ns ns % ps Notes 1 -- 2 3 4, 5
Notes: 1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum operating frequencies. Refer toSection 18.2, "MPX to SYSCLK PLL Ratio", and Section 18.3, "e600 to MPX clock PLL Ratio", for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the short term jitter only and is guaranteed by design. 5. The SYSCLK driver's closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. Note that the frequency modulation for SYSCLK reduces significantly for the spread spectrum source case. This is to guarantee what is supported based on design.
4.1.1
SYSCLK and Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and government requirements. These clock sources intentionally add long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 7 considers short-term (cycle-to-cycle) jitter only and the clock generator's cycle-to-cycle output jitter should meet the MPC8640 input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns, and the MPC8640 is compatible with spread spectrum sources if the recommendations listed in Table 8 are observed.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 15
Input Clocks
Table 8. Spread Spectrum Clock Source Recommendations
At recommended operating conditions. See Table 2. Parameter Frequency modulation Frequency spread Min -- -- Max 50 1.0 Unit kHz % Notes 1 1, 2
Notes: 1. Guaranteed by design. 2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the minimum and maximum specifications given in Table 7.
It is imperative to note that the processor's minimum and maximum SYSCLK, core, and VCO frequencies must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is operated at its maximum rated e600 core frequency should avoid violating the stated limits by using down-spreading only. SDn_REF_CLK and SDn_REF_CLK was designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30-33kHz rate is allowed), assuming both ends have same reference clock. For better results use a source without significant unintended modulation.
4.2
Real Time Clock Timing
The RTC input is sampled by the platform clock (MPX clock). The output of the sampling latch is then used as an input to the counters of the PIC. There is no jitter specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the MPX clock. That is, minimum clock high time is 2 x tMPX, and minimum clock low time is 2 x tMPX. There is no minimum RTC frequency; RTC may be grounded if not needed.
4.3
eTSEC Gigabit Reference Clock Timing
Table 9 provides the eTSEC gigabit reference clocks (EC1_GTX_CLK125 and EC2_GTX_CLK125) AC timing specifications for the MPC8640.
Table 9. ECn_GTX_CLK125 AC Timing Specifications
Parameter/Condition ECn_GTX_CLK125 frequency ECn_GTX_CLK125 cycle time ECn_GTX_CLK125 peak-to-peak jitter Symbol fG125 tG125 tG125J Min -- -- -- Typical 125 100 ppm 8 -- Max -- -- 250 Unit MHz ns ps 1 Notes 3
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 16 Freescale Semiconductor
RESET Initialization
Table 9. ECn_GTX_CLK125 AC Timing Specifications (continued)
ECn_GTX_CLK125 duty cycle GMII, TBI 1000Base-T for RGMII, RTBI tG125H/tG125 45 47 -- 55 53 % 1, 2
Notes: 1. Timing is guaranteed by design and characterization. 2. ECn_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. ECn_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC GTX_CLK. See Section 8.2.6, "RGMII and RTBI AC Timing Specifications" for duty cycle for 10Base-T and 100Base-T reference clock. 3. 100 ppm tolerance on ECn_GTX_CLK125 frequency
NOTE
The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and 4) is no more than 100 ps.
4.4
Platform Frequency Requirements for PCI-Express and Serial RapidIO
The MPX platform clock frequency must be considered for proper operation of the high-speed PCI Express and Serial RapidIO interfaces as described below. For proper PCI Express operation, the MPX clock frequency must be greater than or equal to:
527 MHz x (PCI-Express link width) 16 / (1 + cfg_plat_freq)
Note that at MPX = 400 MHz, cfg_plat_freq = 0 and at MPX > 400 MHz, cfg_plat_freq = 1. Therefore, when operating PCI Express in x8 link width, the MPX platform frequency must be 400 MHz with cfg_plat_freq = 0 or greater than or equal to 527 MHz with cfg_plat_freq = 1. For proper Serial RapidIO operation, the MPX clock frequency must be greater than:
2 x (0.80) x (Serial RapidIO interface frequency) x (Serial RapidIO link width) 64
4.5
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific section of this document.
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8640. Table 10 provides the RESET initialization AC timing specifications.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 17
DDR and DDR2 SDRAM
Table 10. RESET Initialization Timing Specifications
Parameter/Condition Required assertion time of HRESET Minimum assertion time for SRESET_0 & SRESET_1 Platform PLL input setup time with stable SYSCLK before HRESET negation Input setup time for POR configs (other than PLL config) with respect to negation of HRESET Input hold time for all POR configs (including PLL config) with respect to negation of HRESET Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of HRESET Min 100 3 100 4 2 -- Max -- -- -- -- -- 5 Unit s SYSCLKs s SYSCLKs SYSCLKs SYSCLKs 1 2 1 1 1 Notes
Notes: 1. SYSCLK is the primary clock input for the MPC8640. 2 This is related to HRESET assertion time. Stable PLL configuration inputs are required when a stable SYSCLK is applied. See the MPC8641D Integrated Host Processor Reference Manual for more details on the power-on reset sequence.
Table 11 provides the PLL lock times.
Table 11. PLL Lock Times
Parameter/Condition (Platform and E600) PLL lock times Local bus PLL Min -- -- Max 100 50 Unit s s Notes 1
Notes: 1. The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles.
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8640. Note that DDR SDRAM is Dn_GVDD(typ) = 2.5 V and DDR2 SDRAM is Dn_GVDD(typ) = 1.8 V.
6.1
DDR SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8640 when Dn_GVDD(typ) = 1.8 V.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 18 Freescale Semiconductor
DDR and DDR2 SDRAM
Table 12. DDR2 SDRAM DC Electrical Characteristics for Dn_GVDD(typ) = 1.8 V
Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.420 V) Output low current (VOUT = 0.280 V) Symbol Dn_GVDD Dn_MVREF VTT VIH VIL IOZ IOH IOL Min 1.71 0.49 x Dn_GVDD Dn_MVREF - 0.0 4 Dn_MVREF+ 0.1 25 -0.3 -50 -13.4 13.4 Max 1.89 0.51 x Dn_GVDD Dn_MVREF + 0.04 Dn_GVDD + 0.3 Dn_MV REF - 0.125 50 -- -- Unit V V V V V A mA mA 4 Notes 1 2 3
Notes: 1. Dn_GV DD is expected to be within 50 mV of the DRAM Dn_GVDD at all times. 2. Dn_MV REF is expected to be equal to 0.5 x Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver. Peak-to-peak noise on Dn_MVREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to Dn_MVREF. This rail should track variations in the DC level of Dn_MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT Dn_GVDD.
Table 13 provides the DDR2 capacitance when Dn_GVDD(typ) = 1.8 V.
Table 13. DDR2 SDRAM Capacitance for Dn_GVDD(typ)=1.8 V
Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1 1
Note: 1. This parameter is sampled. Dn_GVDD = 1.8 V 0.090 V, f = 1 MHz, TA = 25C, VOUT = Dn_GVDD/2, VOUT (peak-to-peak) = 0.2 V.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 19
DDR and DDR2 SDRAM
Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when Dn_GVDD(typ) = 2.5 V.
Table 14. DDR SDRAM DC Electrical Characteristics for Dn_GVDD (typ) = 2.5 V
Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.95 V) Output low current (VOUT = 0.35 V) Symbol Dn_GVDD Dn_MVREF VTT VIH VIL IOZ IOH IOL Min 2.375 0.49 x Dn_GVDD Dn_MVREF - 0.04 Dn_MVREF + 0.15 -0.3 -50 -16.2 16.2 Max 2.625 0.51 x Dn_GVDD Dn_MV REF + 0.04 Dn_GVDD + 0.3 Dn_MVREF- 0.15 50 -- -- Unit V V V V V A mA mA 4 Notes 1 2 3
Notes: 1. Dn_GV DD is expected to be within 50 mV of the DRAM Dn_GVDD at all times. 2. MVREF is expected to be equal to 0.5 x Dn_GVDD, and to track Dn_GV DD DC variations as measured at the receiver. Peak-to-peak noise on Dn_MVREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to Dn_MVREF. This rail should track variations in the DC level of Dn_MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT Dn_GV DD.
Table 15 provides the DDR capacitance when Dn_GVDD (typ)=2.5 V.
Table 15. DDR SDRAM Capacitance for Dn_GVDD (typ) = 2.5 V
Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1 1
Note: 1. This parameter is sampled. Dn_GVDD = 2.5 V 0.125 V, f = 1 MHz, TA = 25C, VOUT = Dn_GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 16 provides the current draw characteristics for MVREF.
Table 16. Current Draw Characteristics for MVREF
Parameter / Condition Current draw for MVREF Symbol IMVREF Min -- Max 500 Unit A Note 1
1. The voltage regulator for MVREF must be able to supply up to 500 A current.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 20 Freescale Semiconductor
DDR and DDR2 SDRAM
6.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR SDRAM Input AC Timing Specifications
Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Table 17 provides the input AC timing specifications for the DDR2 SDRAM when Dn_GVDD(typ)=1.8 V.
At recommended operating conditions
Parameter AC input low voltage AC input high voltage
Symbol VIL VIH
Min -- Dn_MVREF + 0.25
Max Dn_MVREF - 0.25 --
Unit V V
Notes
Table 18 provides the input AC timing specifications for the DDR SDRAM when Dn_GVDD(typ)=2.5 V.
Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions.
Parameter AC input low voltage AC input high voltage
Symbol VIL VIH
Min -- Dn_MVREF + 0.31
Max Dn_MVREF - 0.31 --
Unit V V
Notes
Table 19 provides the input AC timing specifications for the DDR SDRAM interface.
Table 19. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions.
Parameter Controller Skew for MDQS--MDQ/MECC 533 MHz 400 MHz
Symbol tCISKEW
Min
Max
Unit ps
Notes 1, 2 3
-300 -365
300 365
Note: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called
tDISKEW.This can be determined by the following equation: tDISKEW =+/-(T/4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW.
3. Maximum DDR1 frequency is 400 MHz.
Figure 4 shows the DDR SDRAM input timing for the MDQS to MDQ skew measurement (tDISKEW).
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 21
DDR and DDR2 SDRAM
MCK[n] MCK[n] tMCK
MDQS[n]
MDQ[x]
D0 tDISKEW
D1 tDISKEW
Figure 4. DDR Input Timing Diagram for tDISKEW
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 22 Freescale Semiconductor
DDR and DDR2 SDRAM
6.2.2
DDR SDRAM Output AC Timing Specifications
Table 20. DDR SDRAM Output AC Timing Specifications
At recommended operating conditions.
Parameter MCK[n] cycle time, MCK[n]/MCK[n] crossing MCK duty cycle 533 MHz 400 MHz ADDR/CMD output setup with respect to MCK 533 MHz 400 MHz ADDR/CMD output hold with respect to MCK 533 MHz 400 MHz MCS[n] output setup with respect to MCK 533 MHz 400 MHz MCS[n] output hold with respect to MCK 533 MHz 400 MHz MCK to MDQS Skew MDQ/MECC/MDM output setup with respect to MDQS 533 MHz 400 MHz MDQ/MECC/MDM output hold with respect to MDQS 533 MHz 400 MHz MDQS preamble start
Symbol 1 tMCK tMCKH/tMCK
Min 3 47 47
Max 10 53 53
Unit ns %
Notes 2 8 8
tDDKHAS 1.48 1.95 tDDKHAX 1.48 1.95 tDDKHCS 1.48 1.95 tDDKHCX 1.48 1.95 tDDKHMH tDDKHDS, tDDKLDS 590 700 tDDKHDX, tDDKLDX 590 700 tDDKHMP -0.5 x tMCK - 0.6 -- -- -0.5 x tMCK +0.6 -- -- -0.6 -- -- 0.6 -- -- -- -- -- --
ns
3 7
ns
3 7
ns
3 7
ns
3 7
ns ps
4 5 7
ps
5 7
ns
6
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 23
DDR and DDR2 SDRAM
Table 20. DDR SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions.
Parameter MDQS epilogue end
Symbol 1 tDDKHME
Min -0.6
Max 0.6
Unit ns
Notes 6
Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8641 Integrated Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the symbol conventions described in note 1. 7. Maximum DDR1 frequency is 400 MHz 8. Per the JEDEC spec the DDR2 duty cycle at 400 and 533 MHz is the low and high cycle time values.
NOTE
For the ADDR/CMD setup and hold specifications in Table 20, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied cycle.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 24 Freescale Semiconductor
DDR and DDR2 SDRAM
Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
MCK[n] MCK[n] tMCK tDDKHMHmax) = 0.6 ns
MDQS tDDKHMH(min) = -0.6 ns
MDQS
Figure 5. Timing Diagram for tDDKHMH
Figure 6 shows the DDR SDRAM output timing diagram.
MCK[n] MCK[n] tMCK tDDKHAS ,tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP
Figure 6. DDR SDRAM Output Timing Diagram
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 25
DUART
Figure 7 provides the AC test load for the DDR bus.
Output Z0 = 50 Dn_GVDD/2
RL = 50
Figure 7. DDR AC Test Load
7
7.1
DUART
DUART DC Electrical Characteristics
Table 21. DUART DC Electrical Characteristics
Parameter High-level input voltage Low-level input voltage Input current (VIN 1 = 0 V or VIN = VDD) High-level output voltage (OVDD = min, IOH = -100 A) Low-level output voltage (OVDD = min, IOL = 100 A) Symbol VIH VIL IIN VOH VOL Min 2 - 0.3 -- Max OVDD + 0.3 0.8 5 Unit V V A V
This section describes the DC and AC electrical specifications for the DUART interface of the MPC8640.
Table 21 provides the DC electrical characteristics for the DUART interface.
OVDD - 0.2 --
--
0.2
V
Note: 1. Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
7.2
DUART AC Electrical Specifications
Table 22 provides the AC timing parameters for the DUART interface.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 26 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 22. DUART AC Timing Specifications
Parameter Minimum baud rate Maximum baud rate Oversample rate Value MPX clock/1,048,576 MPX clock/16 16 Unit baud baud -- Notes 1,2 1,3 1,4
Notes: 1. Guaranteed by design. 2. MPX clock refers to the platform clock. 3. Actual attainable baud rate will be limited by the latency of interrupt processing. 4. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample.
8
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
This section provides the AC and DC electrical characteristics for enhanced three-speed and MII management.
8.1
Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1Gb Mbps)--GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics
The electrical characteristics specified here apply to all gigabit media independent interface (GMII), media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals except management data input/output (MDIO) and management data clock (MDC). The RGMII and RTBI interfaces are defined for 2.5 V, while the GMII and TBI interfaces can be operated at 3.3 or 2.5 V. Whether the GMII or TBI interface is operated at 3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII Specification Version 1.2 (3/20/1998). The electrical characteristics for MDIO and MDC are specified in Section 9, "Ethernet Management Interface Electrical Characteristics."
8.1.1
eTSEC DC Electrical Characteristics
All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric attributes specified in Table 23 and Table 24. The potential applied to the input of a GMII, MII, TBI, RGMII, RMII or RTBI receiver may exceed the potential of the receiver's power supply (i.e., a GMII driver powered from a 3.6-V supply driving VOH into a GMII receiver powered from a 2.5-V supply). Tolerance for dissimilar GMII driver and receiver supply potentials is implicit in these specifications. The
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 27
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 23. GMII, MII, RMII, TBI and FIFO DC Electrical Characteristics
Parameter Supply voltage 3.3 V Symbol LVDD TVDD VOH VOL VIH VIL IIH Min 3.135 Max 3.465 Unit V
1, 2
Notes
Output high voltage (LV DD/TVDD = Min, IOH = -4.0 mA) Output low voltage (LV DD/TVDD = Min, IOL = 4.0 mA) Input high voltage Input low voltage Input high current (VIN = LVDD, VIN = TVDD) Input low current (VIN = GND) Notes:
1 2
2.40
--
V
--
0.50
V
2.0 -- --
-- 0.90 40
V V A
1, 2, 3
IIL
-600
--
A
3
LVDD supports eTSECs 1 and 2. TVDD supports eTSECs 3 and 4. 3 The symbol V , in this case, represents the LV and TV symbols referenced in Table 1 and Table 2. IN IN IN
Table 24. GMII, RGMII, RTBI, TBI and FIFO DC Electrical Characteristics
Parameters Supply voltage 2.5 V Symbol LVDD/TVDD Min 2.375 Max 2.625 Unit V
1, 2
Notes
Output high voltage (LVDD/TVDD = Min, IOH = -1.0 mA) Output low voltage (LVDD/TVDD = Min, IOL = 1.0 mA) Input high voltage Input low voltage Input high current (VIN = LVDD, VIN = TVDD) Input low current (VIN = GND) Note:
1 2
VOH VOL VIH VIL IIH
2.00
--
V
--
0.40
V
1.70 -- --
-- 0.90 10
V V A
1, 2, 3
IIL
-15
--
A
3
LVDD supports eTSECs 1 and 2. TVDD supports eTSECs 3 and 4.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 28 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
3
Note that the symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 1 and Table 2.
8.2
FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this section.
8.2.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC's FIFO modes is the double data rate RGMII and RTBI specifications, since they have similar performance and are described in a source-synchronous fashion like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and source clock in GMII fashion. When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn's TSECn_TX_CLK, while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is relationship between the maximum FIFO speed and the platform speed. For more information see Section 18.4.2, "Platform to FIFO Restrictions"
NOTE
The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and 4) is no more than 100 ps. A summary of the FIFO AC specifications appears in Table 25 and Table 26.
Table 25. FIFO Mode Transmit AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V 5% and 2.5 V 5%.
Parameter/Condition TX_CLK, GTX_CLK clock period (GMII mode) TX_CLK, GTX_CLK clock period (Encoded mode) TX_CLK, GTX_CLK duty cycle TX_CLK, GTX_CLK peak-to-peak jitter Rise time TX_CLK (20%-80%) Fall time TX_CLK (80%-20%)
Symbol tFIT tFIT tFITH/tFIT tFITJ tFITR tFITF
Min 8.4 6.4 45 -- -- --
Typ 8.0 8.0 50 -- -- --
Max 100 100 55 250 0.75 0.75
Unit ns ns % ps ns ns
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 29
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 25. FIFO Mode Transmit AC Timing Specification (continued)
At recommended operating conditions with L/TVDD of 3.3 V 5% and 2.5 V 5%.
Parameter/Condition FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
Symbol tFITDV tFITDX
Min 2.0 0.5
Typ -- --
Max -- 3.0
Unit ns ns
Table 26. FIFO Mode Receive AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V 5% and 2.5 V 5%.
Parameter/Condition RX_CLK clock period (GMII mode) RX_CLK clock period (Encoded mode) RX_CLK duty cycle RX_CLK peak-to-peak jitter Rise time RX_CLK (20%-80%) Fall time RX_CLK (80%-20%) RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
1
Symbol tFIR 1 tFIR
1
Min 8.4 6.4 45 -- -- -- 1.5 0.5
Typ 8.0 8.0 50 -- -- -- -- --
Max 100 100 55 250 0.75 0.75 -- --
Unit ns ns % ps ns ns ns ns
tFIRH/tFIR tFIRJ tFIRR tFIRF tFIRDV tFIRDX
100 ppm tolerance on RX_CLK frequency
Timing diagrams for FIFO appear in Figure 8 and Figure 9.
.
tFITF tFIT
tFITR
GTX_CLK
tFITH tFITDV tFITDX
TXD[7:0] TX_EN TX_ER
Figure 8. FIFO Transmit AC Timing Diagram
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 30 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
tFIRR tFIR
RX_CLK
tFIRH tFIRF
RXD[7:0] RX_DV RX_ER
valid data
tFIRDV tFIRDX
Figure 9. FIFO Receive AC Timing Diagram
8.2.2
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
8.2.2.1
GMII Transmit AC Timing Specifications
Table 27. GMII Transmit AC Timing Specifications
Table 27 provides the GMII transmit AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5% and 2.5 V 5%.
Parameter/Condition GMII data TXD[7:0], TX_ER, TX_EN setup time GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK data clock rise time (20%-80%) GTX_CLK data clock fall time (80%-20%)
Symbol 1 tGTKHDV tGTKHDX tGTXR2 tGTXF2
Min 2.5 0.5 -- --
Typ -- -- -- --
Max -- 5.0 1.0 1.0
Unit ns ns ns ns
Notes: 1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 31
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 10 shows the GMII transmit AC timing diagram.
tGTX GTX_CLK tGTXH TXD[7:0] TX_EN TX_ER tGTKHDX tGTKHDV tGTXF tGTXR
Figure 10. GMII Transmit AC Timing Diagram
8.2.2.2
GMII Receive AC Timing Specifications
Table 28. GMII Receive AC Timing Specifications
Table 28 provides the GMII receive AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5% and 2.5 V 5%.
Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time (20%-80%) RX_CLK clock fall time (80%-20%)
Symbol 1 tGRX3 tGRXH/tGRX tGRDVKH tGRDXKH tGRXR
2
Min -- 40 2.0 0.5 -- --
Typ 8.0 -- -- -- -- --
Max -- 60 -- -- 1.0 1.0
Unit ns ns ns ns ns ns
tGRXF2
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design. 3. 100 ppm tolerance on RX_CLK frequency
Figure 11 provides the AC test load for eTSEC.
Output Z0 = 50 RL = 50 LVDD/2
Figure 11. eTSEC AC Test Load
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 32 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 12 shows the GMII receive AC timing diagram.
tGRX RX_CLK tGRXH RXD[7:0] RX_DV RX_ER tGRDXKH tGRDVKH tGRXF tGRXR
Figure 12. GMII Receive AC Timing Diagram
8.2.3
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.3.1
MII Transmit AC Timing Specifications
Table 29. MII Transmit AC Timing Specifications
Table 29 provides the MII transmit AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise time (20%-80%) TX_CLK data clock fall time (80%-20%)
Symbol 1 tMTX2 tMTX tMTXH/tMTX tMTKHDX tMTXR2 tMTXF2
Min -- -- 35 1 1.0 1.0
Typ 400 40 -- 5 -- --
Max -- -- 65 15 4.0 4.0
Unit ns ns % ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design.
Figure 13 shows the MII transmit AC timing diagram.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 33
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF
tMTXR
Figure 13. MII Transmit AC Timing Diagram
8.2.3.2
MII Receive AC Timing Specifications
Table 30. MII Receive AC Timing Specifications
Table 30 provides the MII receive AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time (20%-80%) RX_CLK clock fall time (80%-20%)
Symbol 1 tMRX2,3 tMRX3 tMRXH/tMRX tMRDVKH tMRDXKH tMRXR2 tMRXF2
Min -- -- 35 10.0 10.0 1.0 1.0
Typ 400 40 -- -- -- -- --
Max -- -- 65 -- -- 4.0 4.0
Unit ns ns % ns ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design. 3. 100 ppm tolerance on RX_CLK frequency
Figure 14 provides the AC test load for eTSEC.
Output Z0 = 50 RL = 50 LVDD/2
Figure 14. eTSEC AC Test Load
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 34 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 15 shows the MII receive AC timing diagram.
tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKL tMRXF Valid Data tMRXR
Figure 15. MII Receive AC Timing Diagram
8.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.2.4.1
TBI Transmit AC Timing Specifications
Table 31. TBI Transmit AC Timing Specifications
Table 31 provides the TBI transmit AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5% and 2.5 V 5%.
Parameter/Condition TCG[9:0] setup time GTX_CLK going high TCG[9:0] hold time from GTX_CLK going high GTX_CLK rise time (20%-80%) GTX_CLK fall time (80%-20%)
Symbol 1 tTTKHDV tTTKHDX tTTXR2 tTTXF2
Min 2.0 1.0 -- --
Typ -- -- -- --
Max -- -- 1.0 1.0
Unit ns ns ns ns
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 35
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 16 shows the TBI transmit AC timing diagram.
tTTX GTX_CLK tTTXH tTTXF TCG[9:0] tTTKHDV tTTKHDX tTTXR tTTXF tTTXR
Figure 16. TBI Transmit AC Timing Diagram
8.2.4.2
TBI Receive AC Timing Specifications
Table 32. TBI Receive AC Timing Specifications
Table 32 provides the TBI receive AC timing specifications.
At recommended operating conditions with L/TVDD of 3.3 V 5% and 2.5 V 5%.
Parameter/Condition PMA_RX_CLK[0:1] clock period PMA_RX_CLK[0:1] skew PMA_RX_CLK[0:1] duty cycle RCG[9:0] setup time to rising PMA_RX_CLK RCG[9:0] hold time to rising PMA_RX_CLK PMA_RX_CLK[0:1] clock rise time (20%-80%) PMA_RX_CLK[0:1] clock fall time (80%-20%)
Symbol 1 tTRX3 tSKTRX tTRXH/tTRX tTRDVKH tTRDXKH tTRXR2 tTRXF2
Min
Typ 16.0
Max
Unit ns
7.5 40 2.5 1.5 0.7 0.7
-- -- -- -- -- --
8.5 60 -- -- 2.4 2.4
ns % ns ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Guaranteed by design. 3. 100 ppm tolerance on PMA_RX_CLK[0:1] frequency
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 36 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 17 shows the TBI receive AC timing diagram.
tTRX PMA_RX_CLK1 tTRXH RCG[9:0] tTRDVKH tSKTRX PMA_RX_CLK0 tTRXH tTRDVKH tTRDXKH tTRDXKH tTRXF Valid Data Valid Data tTRXR
Figure 17. TBI Receive AC Timing Diagram
8.2.5
TBI Single-Clock Mode AC Specifications
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1 a 125-MHz TBI receive clock is supplied on TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode, whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied on the TSEC_GTX_CLK125 pin in all TBI modes. A summary of the single-clock TBI mode AC specifications for receive appears in Table 33.
Table 33. TBI single-clock Mode Receive AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V 5% and 2.5 V 5%.
Parameter/Condition RX_CLK clock period RX_CLK duty cycle RX_CLK peak-to-peak jitter Rise time RX_CLK (20%-80%) Fall time RX_CLK (80%-20%) RCG[9:0] setup time to RX_CLK rising edge RCG[9:0] hold time to RX_CLK rising edge
1
Symbol tTRR
1
Min 7.5 40 -- -- -- 2.0 1.0
Typ 8.0 50 -- -- -- -- --
Max 8.5 60 250 1.0 1.0 -- --
Unit ns % ps ns ns ns ns
tTRRH/tTRR tTRRJ tTRRR tTRRF tTRRDVKH tTRRDXKH
100 ppm tolerance on RX_CLK frequency
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 37
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
A timing diagram for TBI receive appears in Figure 18.
.
tTRRR tTRR
RX_CLK
tTRRH RCG[9:0] tTRRF
valid data
tTRRDVKH tTRRDXKH
Figure 18. TBI Single-Clock Mode Receive AC Timing Diagram
8.2.6
RGMII and RTBI AC Timing Specifications
Table 34. RGMII and RTBI AC Timing Specifications
Table 34 presents the RGMII and RTBI AC timing specifications.
At recommended operating conditions with L/TVDD of 2.5 V 5%.
Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock period duration 3 Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%-80%) Fall time (80%-20%)
3, 4 2
Symbol 1 tSKRGT5 tSKRGT tRGT5,6 tRGTH/tRGT5 tRGTR5 tRGTF
5
Min -500 1.0 7.2 40 -- --
Typ 0 -- 8.0 50 -- --
Max 500 2.8 8.8 60 0.75 0.75
Unit ps ns ns % ns ns
Notes: 1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between. 5. Guaranteed by characterization 6. 100 ppm tolerance on RX_CLK frequency
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 38 Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 19 shows the RGMII and RTBI AC timing and multiplexing diagrams.
tRGT tRGTH GTX_CLK (At Transmitter) tSKRGT TXD[8:5][3:0] TXD[7:4][3:0] TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXEN TXD[9] TXERR tSKRGT TX_CLK (At PHY)
TX_CTL
RXD[8:5][3:0] RXD[7:4][3:0]
RXD[8:5] RXD[3:0] RXD[7:4] tSKRGT RXD[4] RXDV RXD[9] RXERR tSKRGT
RX_CTL
RX_CLK (At PHY)
Figure 19. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.2.7
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.7.1
RMII Transmit AC Timing Specifications
Table 35. RMII Transmit AC Timing Specifications
The RMII transmit AC timing specifications are in Table 35.
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%-80%) Fall time REF_CLK (80%-20%)
Symbol 1 tRMT tRMTH/tRMT tRMTJ tRMTR tRMTF
Min
Typ 20.0
Max
Unit ns
35 -- 1.0 1.0
50 -- -- --
65 250 2.0 2.0
% ps ns ns
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 39
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Table 35. RMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition REF_CLK to RMII data TXD[1:0], TX_EN delay
Symbol 1 tRMTDX
Min 1.0
Typ --
Max 10.0
Unit ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 20 shows the RMII transmit AC timing diagram.
tRMT REF_CLK tRMTH TXD[1:0] TX_EN TX_ER tRMTDX tRMTF tRMTR
Figure 20. RMII Transmit AC Timing Diagram
8.2.7.2
RMII Receive AC Timing Specifications
Table 36. RMII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%-80%) Fall time REF_CLK (80%-20%) RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge
Symbol 1 tRMR tRMRH/tRMR tRMRJ tRMRR tRMRF tRMRDV
Min 15.0 35 -- 1.0 1.0 4.0
Typ 20.0 50 -- -- -- --
Max 25.0 65 250 2.0 2.0 --
Unit ns % ps ns ns ns
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 40 Freescale Semiconductor
Ethernet Management Interface Electrical Characteristics
Table 36. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V 5%.
Parameter/Condition RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge
Symbol 1 tRMRDX
Min 2.0
Typ --
Max --
Unit ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 21 provides the AC test load for eTSEC.
Output Z0 = 50 RL = 50 LVDD/2
Figure 21. eTSEC AC Test Load
Figure 22 shows the RMII receive AC timing diagram.
tRMR REF_CLK tRMRH RXD[1:0] CRS_DV RX_ER tRMRDV tRMRDX tRMRF Valid Data tRMRR
Figure 22. RMII Receive AC Timing Diagram
9
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for GMII, RGMII, RMII, TBI and RTBI are specified in "Section 8, "Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management."
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 41
Ethernet Management Interface Electrical Characteristics
9.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 37.
Table 37. MII Management DC Electrical Characteristics
Parameter Supply voltage (3.3 V) Output high voltage (OVDD = Min, IOH = -1.0 mA) Output low voltage (OVDD =Min, IOL = 1.0 mA) Input high voltage Input low voltage Input high current (OVDD = Max, VIN 1 = 2.1 V) Input low current (OVDD = Max, VIN = 0.5 V) Symbol OVDD VOH VOL VIH VIL IIH IIL Min 3.135 2.10 Max 3.465 -- Unit V V
--
0.50
V
1.70 -- --
-- 0.90 40
V V A A
-600
--
Note: 1. Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
9.2
MII Management AC Electrical Specifications
Table 38. MII Management AC Timing Specifications
Table 38 provides the MII management AC timing specifications.
At recommended operating conditions with OVDD is 3.3 V 5%.
Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO valid MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time
Symbol 1 fMDC tMDC tMDCH tMDKHDV tMDKHDX tMDDVKH tMDDXKH tMDCR
Min 2.5 80 32 16*tMPXCLK 10 5 0 --
Typ -- -- --
Max 9.3 400 --
Unit MHz ns ns ns
Notes 2, 4
5 3, 5
-- -- -- --
16*tMPXCLK -- -- 10
ns ns ns ns
4
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 42 Freescale Semiconductor
Ethernet Management Interface Electrical Characteristics
Table 38. MII Management AC Timing Specifications (continued)
At recommended operating conditions with OVDD is 3.3 V 5%.
Parameter/Condition MDC fall time
Symbol 1 tMDHF
Min --
Typ --
Max 10
Unit ns
Notes 4
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency divided by 64.) 3. This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz.) 4. Guaranteed by design. 5. tMPXCLK is the platform (MPX) clock
Figure 23 provides the AC test load for eTSEC.
Output Z0 = 50 RL = 50 OVDD/2
Figure 23. eTSEC AC Test Load
NOTE Output will see a 50 load since what it sees is the transmission line. Figure 24 shows the MII management AC timing diagram.
tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX tMDCF tMDCR
Figure 24. MII Management Interface Timing Diagram
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 43
Local Bus
10 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the MPC8640.
10.1
Local Bus DC Electrical Characteristics
Table 39 provides the DC electrical characteristics for the local bus interface operating at OVDD = 3.3 V DC.
Table 39. Local Bus DC Electrical Characteristics (3.3 V DC)
Parameter High-level input voltage Low-level input voltage Input current (VIN 1 = 0 V or VIN = OVDD) High-level output voltage (OVDD = min, IOH = -2 mA) Low-level output voltage (OVDD = min, IOL = 2 mA) Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- Max OVDD + 0.3 0.8 5 Unit V V A V
OVDD - 0.2 --
--
0.2
V
Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
10.2
Local Bus AC Electrical Specifications
Table 40 describes the timing parameters of the local bus interface at OVDD = 3.3 V with PLL enabled. For information about the frequency range of local bus see Section 18.1, "Clock Ranges."
Table 40. Local Bus Timing Parameters (OVDD = 3.3 V)m - PLL Enabled
Parameter Local bus cycle time Local Bus Duty Cycle LCLK[n] skew to LCLK[m] or LSYNC_OUT Input setup to local bus clock (except LGTA/LUPWAIT) LGTA/LUPWAIT input setup to local bus clock Input hold from local bus clock (except LGTA/LUPWAIT) LGTA/LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Symbol 1 tLBK tLBKH/tLBK tLBKSKEW tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT Min 8 45 -- 1.8 1.7 1.0 1.0 1.5 Max -- 55 150 -- -- -- -- -- Unit ns % ps ns ns ns ns ns 7, 8 3, 4 3, 4 3, 4 3, 4 6 Notes 2
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 44 Freescale Semiconductor
Local Bus
Table 40. Local Bus Timing Parameters (OVDD = 3.3 V)m - PLL Enabled (continued)
Parameter Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high impedance for LAD/LDP Symbol 1 tLBKHOV1 tLBKHOV2 tLBKHOV3 tLBKHOV4 tLBKHOX1 tLBKHOX2 tLBKHOZ1 Min -- -- -- -- 0.7 0.7 -- Max 2.0 2.2 2.3 2.3 -- -- 2.5 Unit ns ns ns ns ns ns ns 3 5 3 Notes
tLBKHOZ2
--
2.5
ns
5
Note: 1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode. 3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL bypass mode to 0.4 x OVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is programmed with the LBCR[AHD] parameter. 7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BVDD/2. 8. Guaranteed by design.
Figure 25 provides the AC test load for the local bus.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 45
Local Bus
Output
Z0 = 50
RL = 50
OVDD/2
Figure 25. Local Bus AC Test Load
Figure 26 to Figure 31 show the local bus signals.
LSYNC_IN tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIVKH2 Input Signal: LGTA tLBIXKH2 tLBIXKH1
LUPWAIT Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV3 Output (Address) Signal: LAD[0:31] tLBOTOT tLBKHOV4 LALE tLBKHOZ2 tLBKHOX2 tLBKHOV1 tLBKHOZ1 tLBKHOX1
tLBKHOV2
tLBKHOZ2 tLBKHOX2
Figure 26. Local Bus Signals (PLL Enabled) NOTE
PLL bypass mode is recommended when LBIU frequency is at or below 83 MHz. When LBIU operates above 83 Mhz, LBIU PLL is recommended to be enabled. Table 41 describes the general timing parameters of the local bus interface at OVDD = 3.3 V with PLL bypassed.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 46 Freescale Semiconductor
Local Bus
Table 41. Local Bus Timing Parameters--PLL Bypassed
Parameter Local bus cycle time Local bus duty cycle Internal launch/capture clock to LCLK delay Input setup to local bus clock (except LGTA/LUPWAIT) LGTA/LUPWAIT input setup to local bus clock Input hold from local bus clock (except LGTA/LUPWAIT) LGTA/LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Symbol 1 tLBK tLBKH/tLBK tLBKHKT tLBIVKH1 tLBIVKL2 tLBIXKH1 tLBIXKL2 tLBOTOT tLBKLOV1 tLBKLOV2 tLBKLOV3 tLBKLOV4 tLBKLOX1 tLBKLOX2 tLBKLOZ1 Min 12 45 2.3 5.7 5.6 -1.8 -1.3 1.5 -- -- -- -- -3.2 -3.2 -- Max -- 55 3.9 -- -- -- -- -- -0.3 -0.1 0 0 -- -- 0.2 Unit ns % ns ns ns ns ns ns ns ns ns ns ns ns ns 4 4 4 4 4 7 8 4, 5 4, 5 4, 5 4, 5 6 Notes 2
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 47
Local Bus
Table 41. Local Bus Timing Parameters--PLL Bypassed (continued)
Parameter Local bus clock to output high impedance for LAD/LDP Symbol 1 tLBKLOZ2 Min -- Max 0.2 Unit ns Notes 7
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK by tLBKHKT. 3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BVDD/2. 4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal in question for 3.3-V signaling levels. 5. Input timings are measured at the pin. 6. The value of tLBOTOT is the measurement of the minimum time between the negation of LALE and any change in LAD 7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. Guaranteed by characterization.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 48 Freescale Semiconductor
Local Bus
Internal launch/capture clock tLBKHKT LCLK[n] tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1
tLBIVKL2 Input Signal: LGTA tLBIXKL2
LUPWAIT tLBKLOV1 Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] tLBKLOV2 Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKLOV3 Output (Address) Signal: LAD[0:31] tLBKLOV4 LALE tLBOTOT tLBKLOX2 tLBKLOX1 tLBKLOZ1
tLBKLOZ2
Figure 27. Local Bus Signals (PLL Bypass Mode)
NOTE In PLL bypass mode, LCLK[n] is the inverted version of the internal clock with the delay of tLBKHKT. In this mode, signals are launched at the rising edge of the internal clock and are captured at falling edge of the internal clock, with the exception of the LGTA/LUPWAIT signal, which is captured at the rising edge of the internal clock.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 49
Local Bus
LSYNC_IN
T1 T3 tLBKHOV1 tLBKHOZ1
GPCM Mode Output Signals: LCS[0:7]/LWE
GPCM Mode Input Signal: LGTA tLBIVKH2 tLBIXKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 tLBIXKH1 tLBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBKHOZ1
Input Signals: LAD[0:31]/LDP[0:3]
Figure 28. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (clock ratio of 4) (PLL Enabled)
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 50 Freescale Semiconductor
Local Bus
Internal launch/capture clock T1 T3
LCLK
tLBKLOV1 GPCM Mode Output Signals: LCS[0:7]/LWE
tLBKLOX1
tLBKLOZ1 GPCM Mode Input Signal: LGTA tLBIVKL2 tLBIXKL2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 29. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (clock ratio of 4) (PLL Bypass Mode)
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 51
Local Bus
LSYNC_IN
T1 T2 T3 T4 tLBKHOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBKHOZ1
GPCM Mode Input Signal: LGTA tLBIVKH2 tLBIXKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 tLBIXKH1
Figure 30. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 or 8 (clock ratio of 8 or 16) (PLL Enabled)
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 52 Freescale Semiconductor
JTAG
Internal launch/capture clock T1 T2 T3 T4
LCLK
tLBKLOV1 GPCM Mode Output Signals: LCS[0:7]/LWE
tLBKLOX1
tLBKLOZ1 GPCM Mode Input Signal: LGTA tLBIVKL2 tLBIXKL2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 31. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 or 8 (clock ratio of 8 or 16) (PLL Bypass Mode)
11 JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8640/D.
11.1
JTAG DC Electrical Characteristics
Table 42 provides the DC electrical characteristics for the JTAG interface.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 53
JTAG
Table 42. JTAG DC Electrical Characteristics
Parameter High-level input voltage Low-level input voltage Input current (VIN 1 = 0 V or VIN = VDD) High-level output voltage (OVDD = min, IOH = -100 A) Low-level output voltage (OVDD = min, IOL = 100 A) Symbol VIH VIL IIN VOH VOL Min 2 - 0.3 -- Max OVDD + 0.3 0.8 5 Unit V V A V
OVDD - 0.2 --
--
0.2
V
Note: 1. Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
11.2
JTAG AC Electrical Specifications
Table 43. JTAG AC Timing Specifications (Independent of SYSCLK) 1
Table 43 provides the JTAG AC timing specifications as defined in Figure 33 through Figure 35.
At recommended operating conditions (see Table 3).
Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO Output hold times: Boundary-scan data TDO JTAG external clock to output high impedance: Boundary-scan data TDO
Symbol 2 fJTG t JTG tJTKHKL tJTGR & tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV tJTKLDX tJTKLOX tJTKLDZ tJTKLOZ
Min 0 30 15 0 25 4 0 20 25 4 4 30 30 3 3
Max 33.3 -- -- 2 -- -- --
Unit MHz ns ns ns ns ns
Notes
6 3 4
ns -- -- ns 20 25 ns -- -- ns 19 9 5, 6 5, 6 5 4
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 54 Freescale Semiconductor
JTAG
Table 43. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)
At recommended operating conditions (see Table 3).
Parameter
Symbol 2
Min
Max
Unit
Notes
Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- load (see Figure 32). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK. 6. Guaranteed by design.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 55
JTAG
Figure 32 provides the AC test load for TDO and the boundary-scan outputs.
Output Z0 = 50 R L = 50 OVDD/2
Figure 32. AC Test Load for the JTAG Interface
Figure 33 provides the JTAG clock input timing diagram.
JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (OVDD/2) VM VM tJTGR tJTGF
Figure 33. JTAG Clock Input Timing Diagram
Figure 34 provides the TRST timing diagram.
TRST VM tTRST VM = Midpoint Voltage (OVDD /2) VM
Figure 34. TRST Timing Diagram
Figure 35 provides the boundary-scan timing diagram.
JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OV DD/2) Output Data Valid Input Data Valid VM
Figure 35. Boundary-Scan Timing Diagram
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 56 Freescale Semiconductor
I2C
12 I2C
This section describes the DC and AC electrical characteristics for the I2C interfaces of the MPC8640.
12.1
I2C DC Electrical Characteristics
Table 44. I2C DC Electrical Characteristics
Table 44 provides the DC electrical characteristics for the I2C interfaces.
At recommended operating conditions with OVDD of 3.3 V 5%.
Parameter Input high voltage level Input low voltage level Low level output voltage Pulse width of spikes which must be suppressed by the input filter Input current each I/O pin (input voltage is between 0.1 x OVDD and 0.9 x OVDD(max) Capacitance for each I/O pin
Symbol VIH VIL VOL tI2KHKL II CI
Min 0.7 x OV DD -0.3 0 0 -10 --
Max OVDD + 0.3 0.3 x OV DD 0.2 x OV DD 50 10 10
Unit V V V ns A pF
Notes
1 2 3
Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. Refer to the MPC8641 Integrated Host Processor Reference Manual for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
12.2
I2C AC Electrical Specifications
Table 45. I2C AC Electrical Specifications
Table 45 provides the AC timing parameters for the I2C interfaces.
All values refer to VIH (min) and VIL (max) levels (see Table 44).
Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data input hold time: CBUS compatible masters I2C bus devices Rise time of both SDA and SCL signals
Symbol 1 fI2C tI2CL 4 tI2CH 4 tI2SVKH 4 tI2SXKL 4 tI2DVKH 4 tI2DXKL
Min 0 1.3 0.6 0.6 0.6 100 -- 02
Max 400 -- -- -- -- -- -- -- 300
Unit kHz s s s s ns
s ns
tI2CR
20 + 0.1 C B5
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 57
I2C
Table 45. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 44).
Parameter Fall time of both SDA and SCL signals Data output delay time Set-up time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis)
Symbol 1
Min 20 + 0.1 Cb 5 -- 0.6 1.3 0.1 x OV DD 0.2 x OV DD
Max 300 0.9 -- -- -- --
3
Unit ns s s s V V
tI2CF
tI2OVKL tI2PVKH tI2KHDX VNL VNH
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. As a transmitter, the MPC8640 provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. When MPC8640 acts as the I2C bus master while transmitting, MPC8640 drives both SCL and SDA. As long as the load on SCL and SDA are balanced, MPC8640 would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for MPC8640 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both the desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock frequency is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of 0x10 (decimal 16): I2C Source Clock Frequency 333 MHz 266 MHz 200 MHz 133 MHz FDR Bit Setting 0x2A 0x05 0x26 0x00 Actual FDR Divider Selected 896 704 512 384 378 KHz 390 KHz 346 KHz Actual I2C SCL Frequency Generated 371 KHz For the detail of I2C frequency calculation, refer to the application note AN2919 "Determining the I2C Frequency Divider Ratio for SCL". Note that the I2C Source Clock Frequency is half of the MPX clock frequency for MPC8640. 3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. Guaranteed by design. 5. CB = capacitance of one bus line in pF.
Figure 32 provides the AC test load for the I2C.
Output Z0 = 50 RL = 50 OVDD/2
Figure 36. I2C AC Test Load
Figure 37 shows the AC timing diagram for the I2C bus.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 58 Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL tI2CH Sr tI2SVKH tI2PVKH P S tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF
Figure 37. I2C Bus AC Timing Diagram
13 High-Speed Serial Interfaces (HSSI)
The MPC8640D features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. The SerDes1 interface is dedicated for PCI Express data transfers. The SerDes2 can be used for PCI Express and/or Serial RapidIO data transfers. This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes Reference Clocks. The SerDes data lane's transmitter and receiver reference circuits are also shown.
13.1
Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. Figure 38 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each signal swings between A Volts and B Volts where A > B. Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. 1. Single-Ended Swing The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and SDn_RX each have a peak-to-peak swing of A - B Volts. This is also referred as each signal wire's Single-Ended Swing. 2. Differential Output Voltage, VOD (or Differential Output Swing): The Differential Output Voltage (or Swing) of the transmitter, VOD, is defined as the difference of the two complimentary output voltages: VSDn_TX - VSDn_TX. The VOD value can be either positive or negative. 3. Differential Input Voltage, VID (or Differential Input Swing):
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 59
High-Speed Serial Interfaces (HSSI)
4.
5.
6.
7.
The Differential Input Voltage (or Swing) of the receiver, VID, is defined as the difference of the two complimentary input voltages: VSDn_RX - VSDn_RX. The VID value can be either positive or negative. Differential Peak Voltage, VDIFFp The peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak Voltage, VDIFFp = |A - B| Volts. Differential Peak-to-Peak, VDIFFp-p Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to -(A - B) Volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak-to-Peak Voltage, VDIFFp-p = 2*VDIFFp = 2 * |(A - B)| Volts, which is twice of differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage can also be calculated as VTX-DIFFp-p = 2*|VOD|. Differential Waveform The differential waveform is constructed by subtracting the inverting signal (SDn_TX, for example) from the non-inverting signal (SDn_TX, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to Figure 47 as an example for differential waveform. Common Mode Voltage, Vcm The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSDn_TX + VSDn_TX)/2 = (A + B) / 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component's output to the other's input. Sometimes, it may be even different between the receiver input and driver output circuits within the same component. It's also referred as the DC offset in some occasion.
A Volts
SDn_TX or SDn_RX
Vcm = (A + B) / 2
B Volts
SDn_TX or SDn_RX
Differential Swing, VID or VOD = A - B Differential Peak Voltage, VDIFFp = |A - B| Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown) Figure 38. Differential Voltage Definitions for Transmitter or Receiver
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 60 Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output's differential swing (VOD) has the same amplitude as each signal's single-ended swing. The differential output signal ranges between 500 mV and -500 mV, in other words, VOD is 500 mV in one phase and -500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
13.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SDn_REF_CLK and SDn_REF_CLK for PCI Express and Serial RapidIO. The following sections describe the SerDes reference clock requirements and some application information.
13.2.1
SerDes Reference Clock Receiver Characteristics
Figure 39 shows a receiver reference diagram of the SerDes reference clocks. * The supply voltage requirements for XVDD_SRDSn are specified in Table 1 and Table 2. * SerDes Reference Clock Receiver Reference Circuit Structure -- The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 39. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50- termination to SGND followed by on-chip AC-coupling. -- The external reference clock driver must be able to drive this termination. -- The SerDes reference clock input can be either differential or single-ended. Refer to the Differential Mode and Single-ended Mode description below for further detailed requirements. * The maximum average current requirement that also determines the common mode voltage range -- When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip. -- This current limitation sets the maximum common mode input voltage to be less than 0.4V (0.4V/50 = 8mA) while the minimum common mode input level is 0.1V above SGND. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA (0-0.8V), such that each phase of the differential input has a single-ended swing from 0V to 800mV with the common mode voltage at 400mV. -- If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 ohms to SGND DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 61
High-Speed Serial Interfaces (HSSI)
*
The input amplitude requirement -- This requirement is described in detail in the following sections.
50 SDn_REF_CLK Input Amp SDn_REF_CLK 50
Figure 39. Receiver of SerDes Reference Clocks
13.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8640D SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. * Differential Mode -- The input amplitude of the differential clock must be between 400mV and 1600mV differential peak-peak (or between 200mV and 800mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800mV and greater than 200mV. This requirement is the same for both external DC-coupled or AC-coupled connection. -- For external DC-coupled connection, as described in section 13.2.1, the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV. Figure 40 shows the SerDes reference clock input requirement for DC-coupled connection scheme. -- For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to SGND. Each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (SGND). Figure 41 shows the SerDes reference clock input requirement for AC-coupled connection scheme. * Single-ended Mode -- The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be between 400mV and 800mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or tied to ground. -- The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 42 shows the SerDes reference clock input requirement for single-ended signaling mode.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 62 Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
-- To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.
SDn_REF_CLK
200mV < Input Amplitude or Differential Peak < 800mV Vmax < 800mV 100mV < Vcm < 400mV
SDn_REF_CLK
Vmin > 0V
Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)
200mV < Input Amplitude or Differential Peak < 800mV SDn_REF_CLK Vmax < Vcm + 400mV Vcm
SDn_REF_CLK
Vmin > Vcm - 400mV
Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)
400mV < SDn_REF_CLK Input Amplitude < 800mV
SDn_REF_CLK 0V SDn_REF_CLK
Figure 42. Single-Ended Reference Clock Input DC Requirements
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 63
High-Speed Serial Interfaces (HSSI)
13.2.3
* *
Interfacing With Other Differential Signaling Levels
*
With on-chip termination to SGND, the differential reference clocks inputs are HCSL (High-Speed Current Steering Logic) compatible DC-coupled. Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling) can be used but may need to be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection. LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. NOTE Figure 43 to Figure 46 below are for conceptual reference only. Due to the fact that clock driver chip's internal structure, output impedance and termination requirements are different between various clock driver chip manufacturers, it's very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the MPC8640D SerDes reference clock receiver requirement provided in this document.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 64 Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8640D SerDes reference clock input's DC requirement.
HCSL CLK Driver Chip
CLK_Out 33 SDn_REF_CLK 50
MPC8640D
Clock Driver 33 CLK_Out
100 differential PWB trace
SerDes Refer. CLK Receiver
SDn_REF_CLK
50
Total 50 . Assume clock driver's output impedance is about 16 .
Clock driver vendor dependent source termination resistor
Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
Figure 44 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver's common mode voltage is higher than the MPC8640D SerDes reference clock input's allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50- termination resistor. It also assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external component.
LVDS CLK Driver Chip
CLK_Out 10 nF SDn_REF_CLK 50
MPC8640D
Clock Driver
100 differential PWB trace
SerDes Refer. CLK Receiver
CLK_Out
10 nF
SDn_REF_CLK
50
Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 65
High-Speed Serial Interfaces (HSSI)
Figure 45 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL driver's DC levels (both common mode voltages and output swing) are incompatible with MPC8640D SerDes reference clock input's DC requirement, AC-coupling has to be used. Figure 45 assumes that the LVPECL clock driver's output impedance is 50. R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140 to 240 depending on clock driver vendor's requirement. R2 is used together with the SerDes reference clock receiver's 50- termination resistor to attenuate the LVPECL output's differential peak level such that it meets the MPC8640D SerDes reference clock's differential input amplitude requirement (between 200mV and 800mV differential peak). For example, if the LVPECL output's differential peak is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip.
LVPECL CLK Driver Chip
CLK_Out R2 10nF SDn_REF_CLK
MPC8640D
50
Clock Driver
R1
100 differential PWB trace R2 10nF SDn_REF_CLK
SerDes Refer. CLK Receiver
CLK_Out R1
50
Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 66 Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8640D SerDes reference clock input's DC requirement.
Single-Ended CLK Driver Chip
Total 50 . Assume clock driver's output impedance is about 16 . 33 CLK_Out SDn_REF_CLK 50
MPC8640D
Clock Driver
100 differential PWB trace
SerDes Refer. CLK Receiver
50
SDn_REF_CLK
50
Figure 46. Single-Ended Connection (Reference Only)
13.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise occurs in the 1-15MHz range. The source impedance of the clock driver should be 50 ohms to match the transmission line and reduce reflections which are a source of noise to the system. Table 46 describes some AC parameters common to PCI Express and Serial RapidIO protocols.
Table 46. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.1V 5% and 1.05V 5%.
Parameter Rising Edge Rate Falling Edge Rate Differential Input High Voltage Differential Input Low Voltage
Symbol Rise Edge Rate Fall Edge Rate VIH VIL
Min 1.0 1.0 +200 --
Max 4.0 4.0
Unit V/ns V/ns mV
Notes 2, 3 2, 3 2 2
-200
mV
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 67
High-Speed Serial Interfaces (HSSI)
Table 46. SerDes Reference Clock Common AC Parameters (continued)
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.1V 5% and 1.05V 5%.
Parameter Rising edge rate (SDn_REF_CLK) to falling edge rate (SDn_REF_CLK) matching
Symbol Rise-Fall Matching
Min --
Max 20
Unit %
Notes 1, 4
Notes: 1. Measurment taken from single ended waveform. 2. Measurment taken from differential waveform. 3. Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 47. 4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 48.
VIH = +200 mV 0.0 V VIL = -200 mV SDn_REF_CLK minus SDn_REF_CLK
Figure 47. Differential Measurement Points for Rise and Fall Time
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
Figure 48. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based on application usage. Refer to the following sections for detailed information: * Section 14.2, "AC Requirements for PCI Express SerDes Clocks" * Section 15.2, "AC Requirements for Serial RapidIO SDn_REF_CLK and SDn_REF_CLK
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 68 Freescale Semiconductor
PCI Express
13.3
SerDes Transmitter and Receiver Reference Circuits
Figure 49 shows the reference circuits for SerDes data lane's transmitter and receiver.
SD1_TXn or SD2_TXn SD1_RXn or SD2_RXn 50 50 SD1_TXn or SD2_TXn SD1_RXn or SD2_RXn 50
50 Transmitter
Receiver
Figure 49. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express or Serial Rapid IO) in this document based on the application usage:" * Section 14, "PCI Express" * Section 15, "Serial RapidIO" Note that external AC Coupling capacitor is required for the above two serial transmission protocols with the capacitor value defined in specification of each protocol section.
14 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8640.
14.1
DC Requirements for PCI Express SDn_REF_CLK and SDn_REF_CLK
For more information, see Section 13.2, "SerDes Reference Clocks."
14.2
AC Requirements for PCI Express SerDes Clocks
Table 47. SDn_REF_CLK and SDn_REF_CLK AC Requirements
Table 47 lists AC requirements.
Symbol tREF tREFCJ tREFPJ REFCLK cycle time
Parameter Description
Min -- -50
Typical 10 -- --
Max 100 50
Units ns ps ps
Notes -- -- --
REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles Phase jitter. Deviation in edge location with respect to mean edge location
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 69
PCI Express
14.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a +/- 300 ppm tolerance.
14.4
Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the Transport and Data Link layer please use the PCI EXPRESS Base Specification. REV. 1.0a document.
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PCI Express
14.4.1
Differential Transmitter (TX) Output
Table 48 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the component pins.
Table 48. Differential Transmitter (TX) Output Specifications
Symbol UI Parameter Unit Interval Min 399.88 Nom 400 Max 400.12 Units ps Comments Each UI is 400 ps 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note 1. VTX-DIFFp-p = 2*|V TX-D+ - VTX-D-| See Note 2.
VTX-DIFFp-p
Differential Peak-to-Peak Output Voltage De- Emphasized Differential Output Voltage (Ratio) Minimum TX Eye Width
0.8
1.2
V
VTX-DE-RATIO
-3.0
-3.5
-4.0
dB
Ratio of the V TX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. See Note 2. The maximum Transmitter jitter can be derived as TTX-MAX-JITTER = 1 - TTX-EYE= 0.3 UI. See Notes 2 and 3. Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. See Notes 2 and 3. See Notes 2 and 5 VTX-CM-ACp = RMS(|VTXD+ - VTXD-|/2 - V TX-CM-DC) VTX-CM-DC = DC(avg) of |VTX-D+ - VTX-D-|/2 See Note 2 |VTX-CM-DC (during LO) - VTX-CM-Idle-DC (During Electrical mV VTX-CM-DC = DC(avg) of |VTX-D+ - VTX-D-|/2 [LO] VTX-CM-Idle-DC = DC (avg) of |VTX-D+ - VTX-D-|/2 [Electrical Idle] See Note 2.
Idle)|<=100
TTX-EYE
0.70
UI
TTX-EYE-MEDIAN-toMAX-JITTER
Maximum time between the jitter median and maximum deviation from the median. D+/D- TX Output 0.125 Rise/Fall Time RMS AC Peak Common Mode Output Voltage Absolute Delta of DC Common Mode Voltage During LO and Electrical Idle 0
0.15
UI
TTX-RISE, TTX-FALL VTX-CM-ACp
UI 20 mV
VTX-CM-DC-ACTIVEIDLE-DELTA
100
mV
VTX-CM-DC-LINE-DELTA Absolute Delta of DC Common Mode between D+ and D- VTX-IDLE-DIFFp Electrical Idle differential Peak Output Voltage
0
25
mV
|VTX-CM-DC-D+ - VTX-CM-DC-D-| <= 25 mV VTX-CM-DC-D+ = DC(avg) of |VTX-D+| VTX-CM-DC-D- = DC(avg) of |VTX-D-| See Note 2. VTX-IDLE-DIFFp = |VTX-IDLE-D+ -VTX-IDLE-D-| <= 20 mV See Note 2.
0
20
mV
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 71
PCI Express
Table 48. Differential Transmitter (TX) Output Specifications (continued)
Symbol VTX-RCV-DETECT Parameter The amount of voltage change allowed during Receiver Detection The TX DC Common Mode Voltage TX Short Circuit Current Limit Minimum time spent in Electrical Idle Maximum time to transition to a valid Electrical idle after sending an Electrical Idle ordered set 50 0 Min Nom Max 600 Units mV Comments The total amount of voltage change that a transmitter can apply to sense whether a low impedance Receiver is present. See Note 6.
VTX-DC-CM
3.6
V
The allowed DC Common Mode voltage under any conditions. See Note 6. The total current the Transmitter can provide when shorted to its ground Minimum time a Transmitter must be in Electrical Idle Utilized by the Receiver to start looking for an Electrical Idle Exit after successfully receiving an Electrical Idle ordered set After sending an Electrical Idle ordered set, the Transmitter must meet all Electrical Idle Specifications within this time. This is considered a debounce time for the Transmitter to meet Electrical Idle after transitioning from LO. Maximum time to meet all TX specifications when transitioning from Electrical Idle to sending differential data. This is considered a debounce time for the TX to meet all TX specifications after leaving Electrical Idle
ITX-SHORT TTX-IDLE-MIN
90
mA UI
TTX-IDLE-SET-TO-IDLE
20
UI
TTX-IDLE-TO-DIFF-DATA Maximum time to transition to valid TX specifications after leaving an Electrical idle condition RLTX-DIFF RLTX-CM ZTX-DIFF-DC ZTX-DC LTX-SKEW CTX Differential Return Loss Common Mode Return Loss DC Differential TX Impedance Transmitter DC Impedance Lane-to-Lane Output Skew AC Coupling Capacitor 75 12 6 80 40 100
20
UI
dB dB 120 500 + 2 UI 200 ps nF
Measured over 50 MHz to 1.25 GHz. See Note 4 Measured over 50 MHz to 1.25 GHz. See Note 4 TX DC Differential mode Low Impedance Required TX D+ as well as D- DC Impedance during all states Static skew between any two Transmitter Lanes within a single Link All Transmitters shall be AC coupled. The AC coupling is required either within the media or within the transmitting component itself.
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PCI Express
Table 48. Differential Transmitter (TX) Output Specifications (continued)
Symbol Tcrosslink Parameter Crosslink Random Timeout Min 0 Nom Max 1 Units ms Comments This random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one Downstream and one Upstream Port. See Note 7.
Notes: 1.) No test load is necessarily associated with this value. 2.) Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 52 and measured over any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 50) 3.) A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4.) The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements is 50 ohms to ground for both the D+ and D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes--see Figure 52). Note that the series capacitors CTX is optional for the return loss measurement. 5.) Measured between 20-80% at transmitter package pins into a test load as shown in Figure 52 for both VTX-D+ and VTX-D-. 6.) See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a 7.) See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a
14.4.2
Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 50 is specified using the passive compliance/test measurement load (see Figure 52) in place of any real PCI Express interconnect + RX component. There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
NOTE
It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (i.e., least squares and median deviation fits).
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 73
PCI Express
Figure 50. Minimum Transmitter Timing and Voltage Output Compliance Specifications
14.4.3
Differential Receiver (RX) Input Specifications
Table 49 defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the component pins.
Table 49. Differential Receiver (RX) Input Specifications
Symbol UI Parameter Unit Interval Min 399.8 8 0.175 Nom 400 Max 400.12 Units ps Comments Each UI is 400 ps 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note 1. VRX-DIFFp-p = 2*|VRX-D+ - VRX-D-| See Note 2. The maximum interconnect media and Transmitter jitter that can be tolerated by the Receiver can be derived as TRX-MAX-JITTER = 1 - TRX-EYE= 0.6 UI. See Notes 2 and 3.
VRX-DIFFp-p
Differential Peak-to-Peak Output Voltage Minimum Receiver Eye Width
1.200
V
TRX-EYE
0.4
UI
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PCI Express
Table 49. Differential Receiver (RX) Input Specifications (continued)
Symbol Parameter Min Nom Max 0.3 Units UI Comments Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. See Notes 2, 3 and 7. VRX-CM-ACp = |VRXD+ - VRXD-|/2 - VRX-CM-DC VRX-CM-DC = DC(avg) of |VRX-D+ - V RX-D-|/2 See Note 2 Measured over 50 MHz to 1.25 GHz with the D+ and D- lines biased at +300 mV and -300 mV, respectively. See Note 4 Measured over 50 MHz to 1.25 GHz with the D+ and D- lines biased at 0 V. See Note 4 RX DC Differential mode impedance. See Note 5 Required RX D+ as well as D- DC Impedance (50 20% tolerance). See Notes 2 and 5. Required RX D+ as well as D- DC Impedance when the Receiver terminations do not have power. See Note 6. VRX-IDLE-DET-DIFFp-p = 2*|VRX-D+ -VRX-D-| Measured at the package pins of the Receiver An unexpected Electrical Idle (V RX-DIFFp-p < VRX-IDLE-DET-DIFFp-p) must be recognized no longer than TRX-IDLE-DET-DIFF-ENTERING to signal an unexpected idle condition.
-JITTER
TRX-EYE-MEDIAN-to-MAX Maximum time between the jitter median and maximum deviation from the median.
VRX-CM-ACp
AC Peak Common Mode Input Voltage Differential Return Loss 15
150
mV
RLRX-DIFF
dB
RLRX-CM ZRX-DIFF-DC ZRX-DC ZRX-HIGH-IMP-DC
Common Mode Return Loss DC Differential Input Impedance DC Input Impedance Powered Down DC Input Impedance Electrical Idle Detect Threshold
6 80 40 200 k 100 50 120 60
dB
VRX-IDLE-DET-DIFFp-p
65
175
mV
TRX-IDLE-DET-DIFFENTERTIME
Unexpected Electrical Idle Enter Detect Threshold Integration Time
10
ms
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PCI Express
Table 49. Differential Receiver (RX) Input Specifications (continued)
Symbol LTX-SKEW Parameter Total Skew Min Nom Max 20 Units ns Comments Skew across all lanes on a Link. This includes variation in the length of SKP ordered set (e.g. COM and one to five Symbols) at the RX as well as any delay differences arising from the interconnect itself.
Notes: 1.) No test load is necessarily associated with this value. 2.) Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 52 should be used as the RX device when taking measurements (also refer to the Receiver compliance eye diagram shown in Figure 51). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 3.) A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 4.) The Receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to 300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 ohms to ground for both the D+ and D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes - see Figure 52). Note: that the series capacitors C TX is optional for the return loss measurement. 5.) Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM) there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port. 6.) The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be measured at 300 mV above the RX ground. 7.) It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data.
14.5
Receiver Compliance Eye Diagrams
The RX eye diagram in Figure 51 is specified using the passive compliance/test measurement load (see Figure 52) in place of any real PCI Express RX component. Note: In general, the minimum Receiver eye diagram measured with the compliance/test measurement load (see Figure 52) will be larger than the minimum Receiver eye diagram measured over a range of systems at the input Receiver of any real PCI Express component. The degraded eye diagram at the input Receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI Express component to vary in impedance from the compliance/test measurement load. The input Receiver eye diagram is implementation specific and is not specified. RX component designer should provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in Figure 51) expected at the input Receiver based on some adequate combination of system simulations and the Return Loss measured looking into the RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram.
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PCI Express
The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
NOTE
The reference impedance for return loss measurements is 50 to ground for both the D+ and D- line (i.e., as measured by a Vector Network Analyzer with 50 probes--see Figure 52). Note that the series capacitors, CTX, are optional for the return loss measurement.
Figure 51. Minimum Receiver Eye Timing and Voltage Compliance Specification
14.5.1
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in Figure 52.
NOTE
The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D- not being exactly matched in length at the package pin boundary.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 77
Serial RapidIO
Figure 52. Compliance Test/Measurement Load
15 Serial RapidIO
This section describes the DC and AC electrical specifications for the RapidIO interface of the MPC8640, for the LP-Serial physical layer. The electrical specifications cover both single and multiple-lane links. Two transmitter types (short run and long run) on a single receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 GBaud. Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to driving two connectors across a backplane. A single receiver specification is given that will accept signals from both the short run and long run transmitter specifications. The short run transmitter specifications should be used mainly for chip-to-chip connections on either the same printed circuit board or across a single connector. This covers the case where connections are made to a mezzanine (daughter) card. The minimum swings of the short run specification reduce the overall power used by the transceivers. The long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. This allows a user to drive signals across two connectors and a backplane. The specifications allow a distance of at least 50 cm at all baud rates. All unit intervals are specified with a tolerance of +/- 100 ppm. The worst case frequency difference between any transmit and receive clock will be 200 ppm. To ensure interoperability between drivers and receivers of different vendors and technologies, AC coupling at the receiver input must be used.
15.1
DC Requirements for Serial RapidIO SDn_REF_CLK and SDn_REF_CLK
For more information, see Section 13.2, "SerDes Reference Clocks."
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 78 Freescale Semiconductor
Serial RapidIO
15.2
AC Requirements for Serial RapidIO SDn_REF_CLK and SDn_REF_CLK
Table 50. SDn_REF_CLK and SDn_REF_CLK AC Requirements
Table 50 lists AC requirements.
Symbol tREF tREFCJ tREFPJ
Parameter Description REFCLK cycle time REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles Phase jitter. Deviation in edge location with respect to mean edge location
Min -- -- -40
Typical Max Units 10(8) -- -- -- 80 40 ns ps ps
Comments 8 ns applies only to serial RapidIO with 125-MHz reference clock --
15.3
Signal Definitions
LP-Serial links use differential signaling. This section defines terms used in the description and specification of differential signals. Figure 53 shows how the signals are defined. The figures show waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal swings between A Volts and B Volts where A > B. Using these waveforms, the definitions are as follows: 8. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a peak-to-peak swing of A - B Volts 9. The differential output signal of the transmitter, VOD, is defined as VTD-VTD 10. The differential input signal of the receiver, VID, is defined as VRD-VRD 11. The differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to -(A - B) Volts 12. The peak value of the differential transmitter output signal and the differential receiver input signal is A - B Volts 13. The peak-to-peak value of the differential transmitter output signal and the differential receiver input signal is 2 * (A - B) Volts
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 79
Serial RapidIO
A Volts
TD or RD
B Volts
TD or RD
Differential Peak-Peak = 2 * (A-B)
Figure 53. Differential Peak-Peak Voltage of Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of the signals TD and TD is 500 mV p-p. The differential output signal ranges between 500 mV and -500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 80 Freescale Semiconductor
Serial RapidIO
15.4
Equalization
With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be used. The most common equalization techniques that can be used are: * A passive high pass filter network placed at the receiver. This is often referred to as passive equalization. * The use of active circuits in the receiver. This is often referred to as adaptive equalization.
15.5
Explanatory Note on Transmitter and Receiver Specifications
AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified in Clause 47 of IEEE 802.3ae-2002. XAUI has similar application goals to serial RapidIO, as described in Section 8.1. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs for XAUI, suitably modified for applications at the baud intervals and reaches described herein.
15.6
Transmitter Specifications
LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section. The differential return loss, S11, of the transmitter in each case shall be better than * -10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz, and * -10 dB + 10log(f/625 MHz) dB for 625 MHz Freq(f) Baud Frequency The reference impedance for the differential return loss measurements is 100 Ohm resistive. Differential return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components related to the driver. The output impedance requirement applies to all valid output levels. It is recommended that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have a minimum value 60 ps. It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB and 15 ps at 3.125 GB.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 81
Serial RapidIO
Table 51. Short Run Transmitter AC Timing Specifications--1.25 GBaud
Range Characteristic Output Voltage, Symbol Min VO -0.40 Max 2.30 Volts Voltage relative to COMMON of either signal comprising a differential pair Unit Notes
Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew
VDIFFPP JD JT SMO
500
1000 0.17 0.35 1000
mV p-p UI p-p UI p-p ps Skew at the transmitter output between lanes of a multilane link +/- 100 ppm
Unit Interval
UI
800
800
ps
Table 52. Short Run Transmitter AC Timing Specifications--2.5 GBaud
Range Characteristic Output Voltage, Symbol Min VO -0.40 Max 2.30 Volts Voltage relative to COMMON of either signal comprising a differential pair Unit Notes
Differential Output Voltage Deterministic Jitter Total Jitter Multiple Output skew
VDIFFPP JD JT SMO
500
1000 0.17 0.35 1000
mV p-p UI p-p UI p-p ps Skew at the transmitter output between lanes of a multilane link +/- 100 ppm
Unit Interval
UI
400
400
ps
Table 53. Short Run Transmitter AC Timing Specifications--3.125 GBaud
Range Characteristic Output Voltage, Symbol Min VO -0.40 Max 2.30 Volts Voltage relative to COMMON of either signal comprising a differential pair Unit Notes
Differential Output Voltage Deterministic Jitter Total Jitter
VDIFFPP JD JT
500
1000 0.17 0.35
mV p-p UI p-p UI p-p
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 82 Freescale Semiconductor
Serial RapidIO
Table 53. Short Run Transmitter AC Timing Specifications--3.125 GBaud (continued)
Range Characteristic Multiple output skew Symbol Min SMO Max 1000 ps Skew at the transmitter output between lanes of a multilane link +/- 100 ppm Unit Notes
Unit Interval
UI
320
320
ps
Table 54. Long Run Transmitter AC Timing Specifications--1.25 GBaud
Range Characteristic Output Voltage, Symbol Min VO -0.40 Max 2.30 Volts Voltage relative to COMMON of either signal comprising a differential pair Unit Notes
Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew
VDIFFPP JD JT SMO
800
1600 0.17 0.35 1000
mV p-p UI p-p UI p-p ps Skew at the transmitter output between lanes of a multilane link +/- 100 ppm
Unit Interval
UI
800
800
ps
Table 55. Long Run Transmitter AC Timing Specifications--2.5 GBaud
Range Characteristic Output Voltage, Symbol Min VO -0.40 Max 2.30 Volts Voltage relative to COMMON of either signal comprising a differential pair Unit Notes
Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew
VDIFFPP JD JT SMO
800
1600 0.17 0.35 1000
mV p-p UI p-p UI p-p ps Skew at the transmitter output between lanes of a multilane link +/- 100 ppm
Unit Interval
UI
400
400
ps
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 83
Serial RapidIO
Table 56. Long Run Transmitter AC Timing Specifications--3.125 GBaud
Range Characteristic Output Voltage, Symbol Min VO -0.40 Max 2.30 Volts Voltage relative to COMMON of either signal comprising a differential pair Unit Notes
Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew
VDIFFPP JD JT SMO
800
1600 0.17 0.35 1000
mV p-p UI p-p UI p-p ps Skew at the transmitter output between lanes of a multilane link +/- 100 ppm
Unit Interval
UI
320
320
ps
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall entirely within the unshaded portion of the Transmitter Output Compliance Mask shown in Figure 54 with the parameters specified in Table 57 when measured at the output pins of the device and the device is driving a 100 Ohm +/-5% differential resistive load. The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the Transmitter Output Compliance Mask when pre-emphasis is disabled or minimized.
Transmitter Differential Output Voltage
VDIFF max
VDIFF min
0
-VDIFF min
-VDIFF max
0
A
B Time in UI
1-B
1-A
1
Figure 54. Transmitter Output Compliance Mask
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 84 Freescale Semiconductor
Serial RapidIO
Table 57. Transmitter Differential Output Eye Diagram Parameters
Transmitter Type 1.25 GBaud short range 1.25 GBaud long range 2.5 GBaud short range 2.5 GBaud long range 3.125 GBaud short range 3.125 GBaud long range VDIFFmin (mV) 250 400 250 400 250 400 VDIFFmax (mV) 500 800 500 800 500 800 A (UI) 0.175 0.175 0.175 0.175 0.175 0.175 B (UI) 0.39 0.39 0.39 0.39 0.39 0.39
15.7
Receiver Specifications
LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section. Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode return loss better than 6 dB from 100 MHz to (0.8)*(Baud Frequency). This includes contributions from on-chip circuitry, the chip package and any off-chip components related to the receiver. AC coupling components are included in this requirement. The reference impedance for return loss measurements is 100 Ohm resistive for differential return loss and 25 Ohm resistive for common mode.
Table 58. Receiver AC Timing Specifications--1.25 GBaud
Range Characteristic Differential Input Voltage Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance Total Jitter Tolerance1 Multiple Input Skew Symbol Min VIN JD JDR JT SMI 200 0.37 0.55 0.65 24 Max 1600 mV p-p UI p-p UI p-p UI p-p ns Measured at receiver Measured at receiver Measured at receiver Measured at receiver Skew at the receiver input between lanes of a multilane link Unit Notes
Bit Error Rate Unit Interval
BER UI 800
10-12 800 ps +/- 100 ppm
Note: 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 85
Serial RapidIO
Table 59. Receiver AC Timing Specifications--2.5 GBaud
Range Characteristic Differential Input Voltage Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance Total Jitter Tolerance1 Multiple Input Skew Symbol Min VIN JD JDR JT SMI 200 0.37 0.55 0.65 24 Max 1600 mV p-p UI p-p UI p-p UI p-p ns Measured at receiver Measured at receiver Measured at receiver Measured at receiver Skew at the receiver input between lanes of a multilane link Unit Notes
Bit Error Rate Unit Interval
BER UI 400
10-12 400 ps +/- 100 ppm
Note: 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
Table 60. Receiver AC Timing Specifications--3.125 GBaud
Range Characteristic Differential Input Voltage Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance Total Jitter Tolerance1 Multiple Input Skew Symbol Min VIN JD JDR JT SMI 200 0.37 0.55 0.65 22 Max 1600 mV p-p UI p-p UI p-p UI p-p ns Measured at receiver Measured at receiver Measured at receiver Measured at receiver Skew at the receiver input between lanes of a multilane link Unit Notes
Bit Error Rate Unit Interval
BER UI 320
10-12 320 ps +/- 100 ppm
Note: 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 86 Freescale Semiconductor
Serial RapidIO
8.5 UI p-p
Sinusoidal Jitter Amplitude
0.10 UI p-p
22.1 kHz Frequency
1.875 MHz
20 MHz
Figure 55. Single Frequency Sinusoidal Jitter Limits
15.8
Receiver Eye Diagrams
For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the corresponding Bit Error Rate specification (Table 58, Table 59, Table 60) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the Receiver Input Compliance Mask shown in Figure 56 with the parameters specified in Table 61. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 Ohm +/- 5% differential resistive load.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 87
Serial RapidIO
VDIFF max
Receiver Differential Input Voltage
VDIFF min 0 -V DIFF min
-V DIFF max
0
A
B
Time (UI)
1-B
1-A
1
Figure 56. Receiver Input Compliance Mask Table 61. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
Receiver Type 1.25 GBaud 2.5 GBaud 3.125 GBaud VDIFFmin (mV) 100 100 100 VDIFFmax (mV) 800 800 800 A (UI) 0.275 0.275 0.275 B (UI) 0.400 0.400 0.400
15.9
Measurement and Test Requirements
Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided by Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE802.3ae-2002 is recommended as a reference for additional information on jitter test methods.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 88 Freescale Semiconductor
Serial RapidIO
15.9.1
Eye Template Measurements
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point at (Baud Frequency)/1667 is applied to the jitter. The data pattern for template measurements is the Continuous Jitter Test Pattern (CJPAT) defined in Annex 48A of IEEE802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10-12. The eye pattern shall be measured with AC coupling and the compliance template centered at 0 Volts differential. The left and right edges of the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100 Ohms resistive +/- 5% differential to 2.5 GHz.
15.9.2
Jitter Test Measurements
For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (Baud Frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter Test Pattern (CJPAT) pattern defined in Annex 48A of IEEE802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured with AC coupling and at 0 Volts differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that described in Annex 48B of IEEE802.3ae.
15.9.3
Transmit Jitter
Transmit jitter is measured at the driver output when terminated into a load of 100 Ohms resistive +/- 5% differential to 2.5 GHz.
15.9.4
Jitter Tolerance
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum of deterministic and random jitter defined in Section 8.6 and then adjusting the signal amplitude until the data eye contacts the 6 points of the minimum eye opening of the receive template shown in Figure 8-4 and Table 8-11. Note that for this to occur, the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter) about the mean zero crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 89
Package
16 Package
This section details package parameters and dimensions.
16.1
Package Parameters for the MPC8640
The package parameters are as provided in the following list. The package type is 33 mm x 33 mm, 1023 pins. There are two package options: high-lead Flip Chip-Ceramic Ball Grid Array (FC-CBGA), and lead-free (FC-CBGA). For all package types: Die size Package outline Interconnects Pitch Total Capacitor count 12.1 mm x 14.7 mm 33 mm x 33 mm 1023 1 mm 43 caps; 100 nF each
For high-lead FC-CBGA (package option: HCTE1 HX) Maximum module height Minimum module height Solder Balls Ball diameter (typical2) 2.97 mm 2.47 mm 89.5% Pb 10.5% Sn 0.60 mm
For RoHS lead-free FC-CBGA (package option: HCTE1 VU) Maximum module height Minimum module height Solder Balls Ball diameter (typical2)
1 2
2.77 mm 2.27 mm 95.5% Sn 4.0% Ag 0.5% Cu 0.60 mm
High-coefficient of thermal expansion Typical ball diameter is before reflow
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 90 Freescale Semiconductor
Package
16.2
Mechanical Dimensions of the MPC8640 FC-CBGA
The mechanical dimensions and bottom surface nomenclature of the MPC8640D (dual core) and MPC8640 (single core) high-lead FC-CBGA (package option: HCTE HX) and lead-free FC-CBGA (package option: HCTE VU) are shown respectfully in Figure 57 and Figure 58.
Figure 57. MPC8640D High-Head FC-CBGA Dimensions
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 91
Package
1. 2. 3. 4. 5. 6. 7. 8.
NOTES for Figure 57 All dimensions are in millimeters. Dimensions and tolerances per ASME Y14.5M-1994. Maximum solder ball diameter measured parallel to datum A. Datum A, the seating plane, is defined by the spherical crowns of the solder balls. Capacitors may not be present on all devices. Caution must be taken not to short capacitors or expose metal capacitor pads on package top. All dimensions symmetrical about centerlines unless otherwise specified. Note that for MPC8640 (single core) the solder balls for the following signals/pins are not populated in the package: VDD_Core1 (R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17, Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24) and SENSEVDD_Core1 (U20).
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 92 Freescale Semiconductor
Package
Figure 58. MPC8640D Lead-Free FC-CBGA Dimensions
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 93
Signal Listings
1. 2. 3. 4. 5. 6. 7. 8.
NOTES for Figure 58 All dimensions are in millimeters. Dimensions and tolerances per ASME Y14.5M-1994. Maximum solder ball diameter measured parallel to datum A. Datum A, the seating plane, is defined by the spherical crowns of the solder balls. Capacitors may not be present on all devices. Caution must be taken not to short capacitors or expose metal capacitor pads on package top. All dimensions symmetrical about centerlines unless otherwise specified. Note that for MPC8640 (single core) the solder balls for the following signals/pins are not populated in the package: VDD_Core1 (R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17, Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24) and SENSEVDD_Core1 (U20).
17 Signal Listings
Table 62 provides the pin assignments for the signals. Notes for the signal changes on the single core device (MPC8640) are italized and prefixed by "S".
Table 62. MPC8640 Signal Reference by Functional Block
Name1 Package Pin Number Pin Type Power Supply Notes
DDR Memory Interface 1 Signals2,3 D1_MDQ[0:63] D15, A14, B12, D12, A15, B15, B13, C13, C11, D11, D9, A8, A12, A11, A9, B9, F11, G12, K11, K12, E10, E9, J11, J10, G8, H10, L9, L7, F10, G9, K9, K8, AC6, AC7, AG8, AH9, AB6, AB8, AE9, AF9, AL8, AM8, AM10, AK11, AH8, AK8, AJ10, AK10, AL12, AJ12, AL14, AM14, AL11, AM11, AM13, AK14, AM15, AJ16, AK18, AL18, AJ15, AL15, AL17, AM17 M8, M7, R8, T10, L11, L10, P9, R10 C14, A10, G11, H9, AD7, AJ9, AM12, AK16, N10 A13, C10, H12, J7, AE8, AM9, AK13, AK17, N9 D14, B10, H13, J8, AD8, AL9, AJ13, AM16, P10 AA8, AA10, T9 Y10, W8, W9, V7, V8, U6, V10, U9, U7, U10, Y9, T6, T8, AE12, R7, P6 AB11 I/O D1_GVDD
D1_MECC[0:7] D1_MDM[0:8] D1_MDQS[0:8] D1_MDQS[0:8] D1_MBA[0:2] D1_MA[0:15] D1_MWE
I/O O I/O I/O O O O
D1_GVDD D1_GVDD D1_GVDD D1_GVDD D1_GVDD D1_GVDD D1_GVDD
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 94 Freescale Semiconductor
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 D1_MRAS D1_MCAS D1_MCS[0:3] D1_MCKE[0:3] D1_MCK[0:5] D1_MCK[0:5] D1_MODT[0:3] D1_MDIC[0:1] D1_MVREF AB12 AC10 AB9, AD10, AC12, AD11 P7, M10, N8, M11 W6, E13, AH11, Y7, F14, AG10 Y6, E12, AH12, AA7, F13, AG11 AC9, AF12, AE11, AF10 E15, G14 AM18 Package Pin Number Pin Type O O O O O O O IO DDR Port 1 reference voltage DDR Memory Interface 2 Signals2,3 D2_MDQ[0:63] A7, B7, C5, D5, C8, D8, D6, A5, C4, A3, D3, D2, A4, B4, C2, C1, E3, E1, H4, G1, D1, E4, G3, G2, J4, J2, L1, L3, H3, H1, K1, L4, AA4, AA2, AD1, AD2, Y1, AA1, AC1, AC3, AD5, AE1, AG1, AG2, AC4, AD4, AF3, AF4, AH3, AJ1, AM1, AM3, AH1, AH2, AL2, AL3, AK5, AL5, AK7, AM7, AK4, AM4, AM6, AJ7 H6, J5, M5, M4, G6, H7, M2, M1 C7, B3, F4, J1, AB1, AE2, AK1, AM5, K6 B6, B1, F1, K2, AB3, AF1, AL1, AL6, L6 A6, A2, F2, K3, AB2, AE3, AK2, AJ6, K5 W5, V5, P3 W1, U4, U3, T1, T2, T3, T5, R2, R1, R5, V4, R4, P1, AH5, P4, N1 Y4 W3 AB5 Y3, AF6, AA5, AF7 I/O D2_GVDD Power Supply D1_GVDD D1_GVDD D1_GVDD D1_GVDD D1_GVDD D1_GVDD D1_GVDD D1_GVDD D1_GVDD /2 27 3 23 Notes
D2_MECC[0:7] D2_MDM[0:8] D2_MDQS[0:8] D2_MDQS[0:8] D2_MBA[0:2] D2_MA[0:15] D2_MWE D2_MRAS D2_MCAS D2_MCS[0:3]
I/O O I/O I/O O O O O O O
D2_GVDD D2_GVDD D2_GVDD D2_GVDD D2_GVDD D2_GVDD D2_GVDD D2_GVDD D2_GVDD D2_GVDD
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 95
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 D2_MCKE[0:3] D2_MCK[0:5] D2_MCK[0:5] D2_MODT[0:3] D2_MDIC[0:1] D2_MVREF Package Pin Number N6, N5, N2, N3 U1, F5, AJ3, V2, E7, AG4 V1, G5, AJ4, W2, E6, AG5 AE6, AG7, AE5, AH6 F8, F7 A18 Pin Type O O O O IO DDR Port 2 reference voltage High Speed I/O Interface 1 (SERDES 1)4 SD1_TX[0:7] SD1_TX[0:7] SD1_RX[0:7] SD1_RX[0:7] SD1_REF_CLK SD1_REF_CLK SD1_IMP_CAL_TX SD1_IMP_CAL_RX SD1_PLL_TPD SD1_PLL_TPA SD1_DLL_TPD SD1_DLL_TPA L26, M24, N26, P24, R26, T24, U26, V24 L27, M25, N27, P25, R27, T25, U27, V25 J32, K30, L32, M30, T30, U32, V30, W32 J31, K29, L31, M29, T29, U31, V29, W31 N32 N31 Y26 J28 U28 T28 N28 P31 O O I I I I Analog Analog O Analog O Analog High Speed I/O Interface 2 (SERDES SD2_TX[0:3] SD2_TX[4:7] SD2_TX[0:3] SD2_TX[4:7] SD2_RX[0:3] SD2_RX[4:7] SD2_RX[0:3] Y24, AA27, AB25, AC27 AE27, AG27, AJ27, AL27 Y25, AA28, AB26, AC28 AE28, AG28, AJ28, AL28 Y30, AA32, AB30, AC32 AH30, AJ32, AK30, AL32 Y29, AA31, AB29, AC31 O O O O I I I 2)4 SVDD SVDD SVDD SVDD SVDD SVDD SVDD 34 32 32, 35 34 SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD 19 30 13, 17 13, 18 13, 17 13, 18 Power Supply D2_GVDD D2_GVDD D2_GVDD D2_GVDD D2_GVDD D2_GVDD /2 27 3 Notes 23
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 96 Freescale Semiconductor
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 SD2_RX[4:7] SD2_REF_CLK SD2_REF_CLK SD2_IMP_CAL_TX SD2_IMP_CAL_RX SD2_PLL_TPD SD2_PLL_TPA SD2_DLL_TPD SD2_DLL_TPA Package Pin Number AH29, AJ31, AK29, AL31 AE32 AE31 AM29 AA26 AF29 AF31 AD29 AD30 Pin Type I I I Analog Analog O Analog O Analog Special Connection Requirement pins No Connects Reserved Reserved Reserved K24, K25, P28, P29, W26, W27, AD25, AD26 H30, R32, V28, AG32 H29, R31, W28, AG31 AD24, AG26 Ethernet Miscellaneous Signals5 EC1_GTX_CLK125 EC2_GTX_CLK125 EC_MDC EC_MDIO AL23 AM23 G31 G32 eTSEC Port 1 TSEC1_TXD[0:7]/ GPOUT[0:7] TSEC1_TX_EN TSEC1_TX_ER TSEC1_TX_CLK TSEC1_GTX_CLK TSEC1_CRS TSEC1_COL TSEC1_RXD[0:7]/ GPIN[0:7] TSEC1_RX_DV Signals5 O LVDD 6, 10 I I O I/O LVDD TVDD OVDD OVDD 39 39 13 14 15 16 Power Supply SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD 19 30 13, 17 13, 18 13, 17 13, 18 Notes 35
AF25, AC23,AG24, AG23, AE24, AE23, AE22, AD22 AB22 AH26 AC22 AH25 AM24 AM25 AL25, AL24, AK26, AK25, AM26, AF26, AH24, AG25 AJ24
O O I O I/O I I I
LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD
36
40 41 37
10
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 97
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 TSEC1_RX_ER TSEC1_RX_CLK AJ25 AK24 eTSEC Port 2 TSEC2_TXD[0:3]/ GPOUT[8:15] TSEC2_TXD[4]/ GPOUT[12] TSEC2_TXD[5:7]/ GPOUT[13:15] TSEC2_TX_EN TSEC2_TX_ER TSEC2_TX_CLK TSEC2_GTX_CLK TSEC2_CRS TSEC2_COL TSEC2_RXD[0:7]/ GPIN[8:15] TSEC2_RX_DV TSEC2_RX_ER TSEC2_RX_CLK AB20, AJ23, AJ22, AD19 Signals5 O LVDD 6, 10 Package Pin Number Pin Type I I Power Supply LVDD LVDD 40 Notes
AH23
O
LVDD
6,10, 38
AH21, AG22, AG21
O
LVDD
6, 10
AB21 AB19 AC21 AD20 AE20 AE21 AL22, AK22, AM21, AH20, AG20, AF20, AF23, AF22 AC19 AD21 AM22 eTSEC Port 3 Signals5
O O I O I/O I I
LVDD LVDD LVDD LVDD LVDD LVDD LVDD
36 6, 38 40 41 37
10
I I I
LVDD LVDD LVDD 40
TSEC3_TXD[0:3] TSEC3_TXD[4]/ TSEC3_TXD[5:7]
AL21, AJ21, AM20, AJ20 AM19 AK21, AL20, AL19
O O O
TVDD TVDD TVDD
6
6
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 98 Freescale Semiconductor
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 TSEC3_TX_EN TSEC3_TX_ER TSEC3_TX_CLK TSEC3_GTX_CLK TSEC3_CRS TSEC3_COL TSEC3_RXD[0:7] TSEC3_RX_DV TSEC3_RX_ER TSEC3_RX_CLK AH19 AH17 AH18 AG19 AE15 AF15 AJ17, AE16, AH16, AH14, AJ19, AH15, AG16, AE19 AG15 AF16 AJ18 eTSEC Port 4 Signals5 TSEC4_TXD[0:3] TSEC4_TXD[4] TSEC4_TXD[5:7] TSEC4_TX_EN TSEC4_TX_ER TSEC4_TX_CLK TSEC4_GTX_CLK TSEC4_CRS TSEC4_COL TSEC4_RXD[0:7] AC18, AC16, AD18, AD17 AD16 AB18, AB17, AB16 AF17 AF19 AF18 AG17 AB14 AC13 AG14, AD13, AF13, AD14, AE14, AB15, AC14, AE17 O O O O O I O I/O I I TVDD TVDD TVDD TVDD TVDD TVDD TVDD TVDD TVDD TVDD 40 41 37 6 25 6 36 Package Pin Number Pin Type O O I O I/O I I I I I Power Supply TVDD TVDD TVDD TVDD TVDD TVDD TVDD TVDD TVDD TVDD 40 40 41 37 Notes 36
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 99
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 TSEC4_RX_DV TSEC4_RX_ER TSEC4_RX_CLK AC15 AF14 AG13 Local Bus Signals5 LAD[0:31] A30, E29, C29, D28, D29, H25, B29, A29, C28, L22, M22, A28, C27, H26, G26, B27, B26, A27, E27, G25, D26, E26, G24, F27, A26, A25, C25, H23, K22, D25, F25, H22 A24, E24, C24, B24 J21, K21, G22, F24, G21 A22, C22, D23, E22, A23 B23 E23 I/O OVDD 6 Package Pin Number Pin Type I I I Power Supply TVDD TVDD TVDD 40 Notes
LDP[0:3] LA[27:31] LCS[0:4] LCS[5]/DMA_DREQ[2] LCS[6]/DMA_DACK[2]
I/O O O O O O O
OVDD OVDD OVDD OVDD OVDD OVDD OVDD
6, 22 6, 22 7 7, 9, 10 7, 10 7, 10 6
LCS[7]/DMA_DDONE[2] F23 LWE[0:3]/ LSDDQM[0:3]/ LBS[0:3] LBCTL LALE LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/ LSDRAS LGPL3/LSDCAS LGPL4/LGTA/ LUPWAIT/LPBSE LGPL5 LCKE E21, F21, D22, E20
D21 E19 F20 H20 J20
O O O O O
OVDD OVDD OVDD OVDD OVDD 25 25
K20 L21 J19 H19
O I/O O O
OVDD OVDD OVDD OVDD
6 42 6
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 100 Freescale Semiconductor
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 LCLK[0:2] LSYNC_IN LSYNC_OUT Package Pin Number G19, L19, M20 M19 D20 DMA Signals5 DMA_DREQ[0:1] DMA_DREQ[2]/LCS[5] DMA_DREQ[3]/IRQ[9] DMA_DACK[0:1] DMA_DACK[2]/LCS[6] DMA_DACK[3]/IRQ[10] DMA_DDONE[0:1] E31, E32 B23 B30 D32, F30 E23 C30 F31, F32 I I I O O O O O O Programmable Interrupt Controller Signals 5 MCP_0 MCP _1 IRQ[0:8] IRQ[9]/DMA_DREQ[3] IRQ[10]/DMA_DACK[3] F17 H17 G28, G29, H27, J23, M23, J27, F28, J24, L23 B30 C30 I I I I I I O DUART Signals5 UART_SIN[0:1] UART_SOUT[0:1] B32, C32 D31, A32 I O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 10 9, 10 9, 10 7, 11 12, S4 OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 10 9, 10 10 9, 10 9, 10 10 Pin Type O I O Power Supply OVDD OVDD OVDD Notes
DMA_DDONE[2]/LCS[7] F23 DMA_DDONE[3]/IRQ[11] D30
IRQ[11]/DMA_DDONE[3] D30 IRQ_OUT J26
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 101
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 UART_CTS[0:1] UART_RTS[0:1] A31, B31 C31, E30 I2C Signals IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL A16 B17 A21 B21 System Control Signals5 HRESET HRESET_REQ SMI_0 SMI_1 SRESET_0 SRESET_1 CKSTP_IN CKSTP_OUT READY/TRIG_OUT B18 K18 L15 L16 C20 C21 L18 L17 J13 Debug Signals5 TRIG_IN TRIG_OUT/READY D1_MSRCID[0:1]/ LB_SRCID[0:1] D1_MSRCID[2]/ LB_SRCID[2] D1_MSRCID[3:4]/ LB_SRCID[3:4] D2_MSRCID[0:4] D1_MDVAL/LB_DVAL J14 J13 F15, K15 K14 H15, G15 E16, C17, F16, H16, K16 J16 I O O O O O O OVDD OVDD OVDD OVDD OVDD OVDD OVDD 10 10, 25 6, 10 10, 25 10 I O I I I I I O O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 7, 11 10, 25 12, S4 12, S4 I/O I/O I/O I/O OVDD OVDD OVDD OVDD 7, 11 7, 11 7, 11 7, 11 Package Pin Number Pin Type I O Power Supply OVDD OVDD Notes
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 102 Freescale Semiconductor
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 D2_MDVAL D19 Power Management Signals5 ASLEEP C19 System Clocking Signals SYSCLK RTC CLK_OUT G16 K17 B16 Test LSSD_MODE TEST_MODE[0:3] C18 C16, E17, D18, D16 JTAG Signals5 TCK TDI TDO TMS TRST H18 J18 G18 F18 A17 Miscellaneous5 Spare GPOUT[0:7]/ TSEC1_TXD[0:7] GPIN[0:7]/ TSEC1_RXD[0:7] GPOUT[8:15]/ TSEC2_TXD[0:7] GPIN[8:15]/ TSEC2_RXD[0:7] J17 AF25, AC23, AG24, AG23, AE24, AE23, AE22, AD22 AL25, AL24, AK26, AK25, AM26, AF26, AH24, AG25 AB20, AJ23, AJ22, AD19, AH23, AH21, AG22, AG21 AL22, AK22, AM21, AH20, AG20, AF20, AF23, AF22 Additional Analog Signals TEMP_ANODE TEMP_CATHODE AA11 Y11 Thermal Thermal Sense, Power and GND Signals SENSEVDD_Core0 M14 VDD_Core0 sensing pin 31 O I O I OVDD OVDD OVDD OVDD 13 6, 10 10 10 10 I I O I I OVDD OVDD OVDD OVDD OVDD 24 23 24 24 Signals5 I I OVDD OVDD 26 26
5
Package Pin Number
Pin Type O
Power Supply OVDD
Notes
O
OVDD
I I O
OVDD OVDD OVDD 32 23
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 103
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 SENSEVDD_Core1 SENSEVSS_Core0 SENSEVSS_Core1 SENSEVDD_PLAT SENSEVSS_PLAT D1_GVDD U20 P14 V20 N18 P18 Package Pin Number Pin Type VDD_Core1 sensing pin Core0 GND sensing pin Core1 GND sensing pin VDD_PLAT sensing pin Platform GND sensing pin SDRAM 1 I/O supply D1_GVDD 2.5 - DDR 1.8 DDR2 Power Supply Notes 12,31, S1 31 12, 31, S3 28 29
B11, B14, D10, D13, F9, F12, H8, H11, H14, K10, K13, L8, P8, R6, U8, V6, W10, Y8, AA6, AB10, AC8, AD12, AE10, AF8, AG12, AH10, AJ8, AJ14, AK12, AL10, AL16 B2, B5, B8, D4, D7, E2, F6, G4, H2, J6, K4, L2, M6, N4, P2, T4, U2, W4, Y2, AB4, AC2, AD6, AE4, AF2, AG6, AH4, AJ2, AK6, AL4, AM2 B22, B25, B28, D17, D24, D27, F19, F22, F26, F29, G17, H21, H24, K19, K23, M21, AM30
D2_GVDD
SDRAM 2 I/O supply
D2_GVDD 2.5 V - DDR 1.8 V - DDR2
OVDD
DUART, Local Bus, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, JTAG, Power management, I2C, JTAG and Miscellaneous I/O voltage TSEC1 and TSEC2 I/O voltage TSEC3 and TSEC4 I/O voltage Transceiver Power Supply SerDes Serial I/O Power Supply for SerDes Port 1
OVDD
3.3 V
LVDD
AC20, AD23, AH22
LVDD 2.5/3.3 V TVDD 2.5/3.3 V
TVDD
AC17, AG18, AK20
SVDD
H31, J29, K28, K32, L30, M28, M31, N29, R30, T31, U29, V32, W30, Y31, AA29, AB32, AC30, AD31, AE29, AG30, AH31, AJ29, AK32, AL30, AM31 K26, L24, M27, N25, P26, R24, R28, T27, U25, V26
SVDD 1.05/1.1 V XVDD_SRDS1 1.05/1.1 V
XVDD_SRDS1
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 104 Freescale Semiconductor
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 XVDD_SRDS2 Package Pin Number AA25, AB28, AC26, AD27, AE25, AF28, AH27, AK28, AM27, W24, Y27 Pin Type Serial I/O Power Supply for SerDes Port 2 Core 0 voltage supply Power Supply XVDD_SRDS2 1.05/1.1 V VDD_Core0 0.95/1.05/1.1 V Core 1 voltage supply VDD_Core1 0.95/1.05/1.1 V Platform supply voltage Core 0 PLL Supply Core 1 PLL Supply Platform PLL supply voltage Local Bus PLL supply voltage SerDes Port 1 PLL & DLL Power Supply SerDes Port 2 PLL & DLL Power Supply GND VDD_PLAT 1.05/1.1 V AVDD_Core0 0.95/1.05/1.1 V AVDD_Core1 0.95/1.05/1.1 V AV DD_PLAT 1.05/1.1 V AVDD_LB 1.05/1.1 V AVDD_SRDS1 1.05/1.1 V AVDD_SRDS2 1.05/1.1 V 12, S2 12, S1 Notes
VDD_Core0
L12, L13, L14, M13, M15, N12, N14, P11, P13, P15, R12, R14, T11, T13, T15, U12, U14, V11, V13, V15, W12, W14, Y12, Y13, Y15, AA12, AA14, AB13 R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17, Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24 M16, M17, M18, N16, N20, N22, P17, P19, P21, P23, R22 B20
VDD_Core1
VDD_PLAT AVDD_Core0
AVDD_Core1
A19
AV DD_PLAT AVDD_LB AV DD_SRDS1
B19 A20 P32
AV DD_SRDS2
AF32
GND
C3, C6, C9, C12, C15, C23, C26, E5, E8, E11, E14, E18, E25, E28, F3, G7, G10, G13, G20, G23, G27, G30, H5, J3, J9, J12, J15, J22, J25, K7, L5, L20, M3, M9, M12, N7, N11, N13, N15, N17, N19, N21, N23, P5, P12, P16, P20, P22, R3, R9, R11, R13, R15, R17, R19, R21, R23, T7, T12, T14, T16, T18, T20, T22, U5, U11,U13, U15, U17, U19, U21, U23, V3, V9, V12, V14, V16, V18, V22, W7, W11, W13, W15, W17, W19, W21, W23,Y5, Y14, Y16, Y18, Y20, Y22, AA3, AA9, AA13, AA15, AA17, AA19, AA21, AA23, AB7, AB24, AC5, AC11, AD3, AD9, AD15, AE7, AE13, AE18, AF5, AF11, AF21, AF24, AG3, AG9, AH7, AH13, AJ5, AJ11, AK3, AK9, AK15, AK19, AK23, AL7, AL13
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 105
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 AGND_SRDS1 P30 Package Pin Number Pin Type SerDes Port 1 Ground pin for AVDD_SRDS1 SerDes Port 2 Ground pin for AVDD_SRDS2 Power Supply Notes
AGND_SRDS2
AF30
-
SGND
Ground pins for H28, H32, J30, K31, L28, L29, M32, N30, SVDD R29, T32, U30, V31, W29,Y32 AA30, AB31, AC29, AD32, AE30, AG29, AH32, AJ30, AK31, AL29, AM32 K27, L25, M26, N24, P27, R25, T26, U24, V27, W25, Y28, AA24, AB27, AC25, AD28, AE26, AF27, AH28, AJ26, AK27, AL26, AM28 Ground pins for XVDD_SRDSn
XGND
Reset Configuration Signals20 TSEC1_TXD[0] / cfg_alt_boot_vec TSEC1_TXD[1]/ cfg_platform_freq TSEC1_TXD[2:4]/ cfg_device_id[5:7] TSEC1_TXD[5]/ cfg_tsec1_reduce TSEC1_TXD[6:7]/ cfg_tsec1_prtcl[0:1] TSEC2_TXD[0:3]/ cfg_rom_loc[0:3] TSEC2_TXD[4], TSEC2_TX_ER/ cfg_dram_type[0:1] TSEC2_TXD[5]/ cfg_tsec2_reduce TSEC2_TXD[6:7]/ cfg_tsec2_prtcl[0:1] TSEC3_TXD[0:1]/ cfg_spare[0:1] TSEC3_TXD[2]/ cfg_core1_enable TSEC3_TXD[3]/ cfg_core1_lm_offset AC23 AG24, AG23, AE24 AE23 AE22, AD22 AB20, AJ23, AJ22, AD19 AH23, AB19 AH21 AG22, AG21 AL21, AJ21 AM20 AJ20 LVDD LVDD LVDD LVDD LVDD LVDD 38 21 AF25 LVDD
O O -
LVDD LVDD TVDD TVDD LVDD 33
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 106 Freescale Semiconductor
Signal Listings
Table 62. MPC8640 Signal Reference by Functional Block (continued)
Name1 TSEC3_TXD[5]/ cfg_tsec3_reduce TSEC3_TXD[6:7]/ cfg_tsec3_prtcl[0:1] TSEC4_TXD[0:3]/ cfg_io_ports[0:3] TSEC4_TXD[5]/ cfg_tsec4_reduce TSEC4_TXD[6:7]/ cfg_tsec4_prtcl[0:1] LAD[0:31]/ cfg_gpporcr[0:31] AK21 AL20, AL19 AC18, AC16, AD18, AD17 AB18 AB17, AB16 A30, E29, C29, D28, D29, H25, B29, A29, C28, L22, M22, A28, C27, H26, G26, B27, B26, A27, E27, G25, D26, E26, G24, F27, A26, A25, C25, H23, K22, D25, F25, H22 E21 F21 D22, E20 A24, E24, C24, B24, J21 K21, G22, F24, G21 K20, J19 F15 K15 Package Pin Number Pin Type Power Supply LVDD LVDD LVDD LVDD LVDD OVDD Notes
LWE[0]/ cfg_cpu_boot LWE[1]/ cfg_rio_sys_size LWE[2:3]/ cfg_host_agt[0:1] LDP[0:3], LA[27] / cfg_core_pll[0:4] LA[28:31]/ cfg_sys_pll[0:3] LGPL[3], LGPL[5]/ cfg_boot_seq[0:1] D1_MSRCID[0]/ cfg_mem_debug D1_MSRCID[1]/ cfg_ddr_debug
-
OVDD OVDD OVDD OVDD OVDD OVDD 22
-
22
-
OVDD OVDD
Note: 1. Multi-pin signals such as D1_MDQ[0:63] and D2_MDQ[0:63] have their physical package pin numbers listed in order corresponding to the signal names. 2. Stub Series Terminated Logic (SSTL-18 and SSTL-25) type pins. 3. If a DDR port is not used, it is possible to leave the related power supply (Dn_GVDD, Dn_MVREF) turned off at reset. Note that these power supplies can only be powered up again at reset for functionality to occur on the DDR port. 4. Low Voltage Differential Signaling (LVDS) type pins. 5. Low Voltage Transistor-Transistor Logic (LVTTL) type pins. 6. This pin is a reset configuration pin and appears again in the Reset Configuration Signals section of this table. See the Reset Configuration Signals section of this table for config name and connection details. 7. Recommend a weak pull-up resistor (1-10 k) be placed from this pin to its power supply. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 107
Signal Listings
8. Recommend a weak pull-down resistor (2-10 k) be placed from this pin to ground. 9. This multiplexed pin has input status in one mode and output in another 10. This pin is a multiplexed signal for different functional blocks and appears more than once in this table. 11. This pin is open drain signal. 12. Functional only on the MPC8640D. 13. These pins should be left floating. 14. These pins should be connected to SV DD. 15. These pins should be pulled to ground with a strong resistor (270- to 330-). 16. These pins should be connected to OVDD. 17.This is a SerDes PLL/DLL digital test signal and is only for factory use. 18. This is a SerDes PLL/DLL analog test signal and is only for factory use. 19. This pin should be pulled to ground with a 100- resistor. 20. The pins in this section are reset configuration pins. Each pin has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pullup or active driver is needed. 21. Should be pulled down at reset if platform frequency is at 400 MHz. 22. These pins require 4.7-k pull-up or pull-down resistors and must be driven as they are used to determine PLL configuration ratios at reset. 23. This output is actively driven during reset rather than being tri-stated during reset. 24 These JTAG pins have weak internal pull-up P-FETs that are always enabled. 25. This pin should NOT be pulled down (or driven low) during reset. 26.These are test signals for factory use only and must be pulled up (100- to 1- k.) to OVDD for normal machine operation. 27. Dn_MDIC[0] should be connected to ground with an 18- resistor +/- 1- and Dn_MDIC[1] should be connected Dn_GVDD with an 18- resistor +/- 1-. These pins are used for automatic calibration of the DDR IOs. 28. Pin N18 is recommended as a reference point for determining the voltage of VDD_PLAT and is hence considered as the VDD_PLAT sensing voltage and is called SENSEVDD_PLAT. 29. Pin P18 is recommended as the ground reference point for SENSEVDD_PLAT and is called SENSEVSS_PLAT. 30.This pin should be pulled to ground with a 200- resistor. 31.These pins are connected to the power/ground planes internally and may be used by the core power supply to improve tracking and regulation. 32. Must be tied low if unused 33. These pins may be used as defined functional reset configuration pins in the future. Please include a resistor pull up/down option to allow flexibility of future designs. 34. Used as serial data output for SRIO 1x/4x link. 35. Used as serial data input for SRIO 1x/4x link. 36.This pin requires an external 4.7-k pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. 37.This pin is only an output in FIFO mode when used as Rx Flow Control. 38.This pin functions as cfg_dram_type[0 or 1] at reset and MUST BE VALID BEFORE HRESET ASSERTION in device sleep mode. 39. Should be pulled to ground if unused (such as in FIFO, MII and RMII modes). 40. See Section 18.4.2, "Platform to FIFO Restrictions" for clock speed limitations for this pin when used in FIFO mode. 41. The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and 4) is no more than 100 ps. 42. For systems which boot from Local Bus (GPCM)-controlled flash, a pullup on LGPL4 is required. Special Notes for Single Core Device: S1. Solder ball for this signal will not be populated in the single core package. S2. The PLL filter from VDD_Core1 to AVDD_Core1 should be removed. AVDD_Core1 should be pulled to ground with a weak (2-10 k) resistor. See Section 20.2.1, "PLL Power Supply Filtering" for more details.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 108 Freescale Semiconductor
Clocking
S3. This pin should be pulled to GND for the single core device. S4. No special requirement for this pin on single core device. Pin should be tied to power supply as directed for dual core.
18 Clocking
This section describes the PLL configuration of the MPC8640. Note that the platform clock is identical to the MPX clock.
18.1
Clock Ranges
Table 63 provides the clocking specifications for the processor cores and Table 64 provides the clocking specifications for the memory bus. Table 65 provides the clocking for the Platform/MPX bus and Table 66 provides the clocking for the Local bus.
Table 63. Processor Core Clocking Specifications
Maximum Processor Core Frequency Characteristic 1000 MHz Min e600 core processor frequency 800 Max 1000 1067 MHz Min 800 Max 1067 1250MHz Min 800 Max 1250 MHz 1, 2 Unit Notes
Notes: 1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 18.2, "MPX to SYSCLK PLL Ratio," and Section 18.3, "e600 to MPX clock PLL Ratio," for ratio settings. 2. The minimum e600 core frequency is based on the minimum platform clock frequency of 400 MHz.
Table 64. Memory Bus Clocking Specifications
Maximum Processor Core Frequency Characteristic 1000, 1067, 1250 MHz Min Memory bus clock frequency 200 Max 266 MHz 1, 2 Unit Notes
Notes: 1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 18.2, "MPX to SYSCLK PLL Ratio," and Section 18.3, "e600 to MPX clock PLL Ratio," for ratio settings. 2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock frequency.
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Table 65. Platform/MPX bus Clocking Specifications
Maximum Processor Core Frequency Characteristic 1000, 1067, 1250 MHz Min Platform/MPX bus clock frequency 400 Max 533 MHz 1, 2 Unit Notes
Notes: 1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 18.2, "MPX to SYSCLK PLL Ratio," and Section 18.3, "e600 to MPX clock PLL Ratio," for ratio settings. 2. Platform/MPX frequencies between 400 and 500 MHz are not supported.
Table 66. Local Bus Clocking Specifications
Maximum Processor Core Frequency Characteristic 1000, 1067, 1250 MHz Min Local bus clock speed (for Local Bus Controller) 25 Max 133 MHz 1 Unit Notes
Notes: 1. The Local bus clock speed on LCLK[0:2] is determined by MPX clock divided by the Local Bus PLL ratio programmed in LCRR[CLKDIV]. See the reference manual for the MPC8641D for more information on this.
18.2
MPX to SYSCLK PLL Ratio
The MPX clock is the clock that drives the MPX bus, and is also called the platform clock. The frequency of the MPX is set using the following reset signals, as shown in Table 67: * SYSCLK input signal * Binary value on LA[28:31] at power up Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note that the DDR data rate is the determining factor in selecting the MPX bus frequency, since the MPX frequency must equal the DDR data rate.
Table 67. MPX:SYSCLK Ratio Binary Value of LA[28:31] Signals 0000 0001
MPX:SYSCLK Ratio
Reserved Reserved
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 110 Freescale Semiconductor
Clocking
Table 67. MPX:SYSCLK Ratio Binary Value of LA[28:31] Signals 0010 0011 0100 0101 0110 0111 1000 1001
MPX:SYSCLK Ratio
2:1 3:1 4:1 5:1 6:1 Reserved 8:1 Reserved
18.3
e600 to MPX clock PLL Ratio
Table 68 describes the clock ratio between the platform and the e600 core clock. This ratio is determined by the binary value of LDP[0:3], LA[27](cfg_core_pll[0:4] - reset config name) at power up, as shown in Table 68.
Table 68. e600 Core to MPX Clock Ratio
Binary Value of LDP[0:3], LA[27] Signals 01000 01100 10000 11100 10100 01110 e600 core: MPX Clock Ratio 2:1 2.5:1 3:1 Reserved Reserved Reserved
18.4
18.4.1
Frequency Options
SYSCLK to Platform Frequency Options
Table 69 shows some SYSCLK frequencies and the expected MPX frequency values based on the MPX clock to SYSCLK ratio. Note that frequencies between 400 MHz and 500 MHz are NOT supported on the
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platform. See note regarding cfg_platform_freq in Section 17, "Signal Listings" since it is a reset configuration pin that is related to platform frequency.
Table 69. Frequency Options of SYSCLK with Respect to Platform/MPX Clock Speed
MPX to SYSCLK Ratio 66 83
SYSCLK (MHz)
100
133
167
Platform/MPX Frequency (MHz) 1 2 3 4 5 6 8
1
400 400 500 400 533 500 533
500
SYSCLK frequency range is 66-167 MHz. Platform clock/ MPX frequency range is 400 MHz, 500-533 MHz.
18.4.2
Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed. For FIFO GMII mode: FIFO TX/RX clock frequency <= platform clock frequency / 4.2 For example, if the platform frequency is 500 MHz, the FIFO TX/RX clock frequency should be no more than 119 MHz For FIFO encoded mode: FIFO TX/RX clock frequency <= platform clock frequency / 3.2 For example, if the platform frequency is 500 MHz, the FIFO TX/RX clock frequency should be no more than 156 MHz
19 Thermal
This section describes the thermal specifications of the MPC8640.
19.1
Thermal Characteristics
Table 70 provides the package thermal characteristics for the MPC8640.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 112 Freescale Semiconductor
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Table 70. Package Thermal Characteristics1
Characteristic Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board Junction-to-board thermal resistance Junction-to-case thermal resistance Symbol RJA RJA RJMA RJMA RJB RJC Value 18 13 13 9 5 < 0.1 Unit C/W C/W C/W C/W C/W C/W Notes 1, 2 1, 3 1, 3 1, 3 4 5
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. This is the thermal resistance between die and case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1 C/W.
19.2 Thermal Management Information
This section provides thermal management information for the high coefficient of thermal expansion (HCTE) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design--the heat sink, airflow, and thermal interface material. The MPC8640 implements several features designed to assist with thermal management, including the temperature diode. The temperature diode allows an external device to monitor the die temperature in order to detect excessive temperature conditions and alert the system; see Section 19.2.4, "Temperature Diode," for more information. To reduce the die-junction temperature, heat sinks are required; due to the potential large mass of the heat sink, attachment through the printed-circuit board is suggested. In any implementation of a heat sink solution, the force on the die should not exceed ten pounds force (45 newtons). Figure 59 and Figure 52 show a spring clip through the board. Occasionally the spring clip is attached to soldered hooks or to a plastic backing structure. Screw and spring arrangements are also frequently used.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 113
Thermal
Heat Sink Heat Sink Clip Thermal Interface Material
HCTE FC-CBGA Package
Printed-Circuit Board
Figure 59. FC-CBGA Package Exploded Cross-Sectional View with Several Heat Sink Options
There are several commercially-available heat sinks for the MPC8640 provided by the following vendors: Aavid Thermalloy 603-224-9988 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Advanced Thermal Solutions 781-769-2800 89 Access Road #27. Norwood, MA02062 Internet: www.qats.com Alpha Novatech 408-749-7601 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com Calgreg Thermal Solutions 888-732-6100 60 Alhambra Road, Suite 1 Warwick, RI 02886 Internet: www.calgreg.com International Electronic Research Corporation (IERC)818-842-7277 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Millennium Electronics (MEI) 408-436-8770 Loroco Sites 671 East Brokaw Road San Jose, CA 95112 Internet: www.mei-thermal.com
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 114 Freescale Semiconductor
Thermal
Tyco Electronics Chip CoolersTM P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com
800-522-6752
603-635-5102
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
19.2.1
Internal Package Conduction Resistance
For the exposed-die packaging technology described in Table 70, the intrinsic conduction thermal resistance paths are as follows: * The die junction-to-case thermal resistance (the case is actually the top of the exposed silicon die) * The die junction-to-board thermal resistance
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 115
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Figure 60 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
External Resistance Radiation Convection
Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads
Printed-Circuit Board
External Resistance
Radiation
Convection
(Note the internal versus external package resistance.)
Figure 60. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Heat generated on the active side of the chip is conducted through the silicon, through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. Because the silicon thermal resistance is quite small, the temperature drop in the silicon may be neglected for a first-order analysis. Thus the thermal interface material and the heat sink conduction/convective thermal resistances are the dominant terms.
19.2.2
Thermal Interface Materials
A thermal interface material is recommended at the package-to-heat sink interface to minimize the thermal contact resistance. Figure 61 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 59). Therefore, synthetic grease offers the best thermal performance, considering the low interface pressure, and is recommended due to the high power dissipation of the MPC8640. Of course, the selection of any thermal interface material depends on many factors--thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, and so on.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 116 Freescale Semiconductor
Thermal
2
Silicone Sheet (0.006 in.) Bare Joint Fluoroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease
Specific Thermal Resistance (K-in.2/W)
1.5
1
0.5
0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi)
Figure 61. Thermal Performance of Select Thermal Interface Material
The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based on high conductivity and mechanical strength to meet equipment shock/vibration requirements. There are several commercially available thermal interfaces and adhesive materials provided by the following vendors: The Bergquist Company 800-347-4572 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com Chomerics, Inc. 781-935-4850 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation 800-248-2481 Corporate Center PO Box 994 Midland, MI 48686-0994 Internet: www.dowcorning.com
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 117
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Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com
888-642-7674
888-246-9050
The following section provides a heat sink selection example using one of the commercially available heat sinks.
19.2.3 Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = Ti + Tr + (RJC + Rint + Rsa) x Pd where: Tj is the die-junction temperature Ti is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet RJC is the junction-to-case thermal resistance Rint is the adhesive or interface material thermal resistance Rsa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in Table 2. The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ti) may range from 30 to 40C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to 10C. The thermal resistance of the thermal interface material (Rint) is typically about 0.2C/W. For example, assuming a Ti of 30C, a Tr of 5C, a package RJC = 0.1, and a typical power consumption (Pd) of 43.4 W, the following expression for Tj is obtained: Die-junction temperature: Tj = 30C + 5C + (0.1C/W + 0.2C/W + sa) x 43.4 W For this example, a Rsavalue of 1.32 C/W or less is required to maintain the die junction temperature below the maximum value of Table 2. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature--airflow, board population (local
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 118 Freescale Semiconductor
Thermal
heat flux of adjacent components), heat sink efficiency, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, and so on. Due to the complexity and variety of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board as well as system-level designs. For system thermal modeling, the MPC8640 thermal model is shown in Figure 62. Four cuboids are used to represent this device. The die is modeled as 12.4x15.3 mm at a thickness of 0.86 mm. See Section 3, "Power Characteristics" for power dissipation details. The substrate is modeled as a single block 33x33x1.2 mm with orthotropic conductivity: 13.5 W/(m * K) in the xy-plane and 5.3 W/(m * K) in the z-direction. The die is centered on the substrate. The bump/underfill layer is modeled as a collapsed thermal resistance between the die and substrate with a conductivity of 5.3 W/(m * K) in the thickness dimension of 0.07 mm. Because the bump/underfill is modeled with zero physical dimension (collapsed height), the die thickness was slightly enlarged to provide the correct height. The C5 solder layer is modeled as a cuboid with dimensions 33x33x0.4 mm and orthotropic thermal conductivity of 0.034 W/(m * K) in the xy-plane and 9.6 W/(m * K) in the z-direction. An LGA solder layer would be modeled as a collapsed thermal resistance with thermal conductivity of 9.6W/(m * K) and an effective height of 0.1 mm. The thermal model uses approximate dimensions to reduce grid. Please refer to the case outline for actual dimensions.
Conductivity Value Unit Die z Silicon Temperature dependent Bump and Underfill Substrate C5 solder layer Side View of Model (Not to Scale) x
Die (12.4x15.3x0.86 mm)
Bump and Underfill (12.4 x 15.3 x 0.07 mm) Collapsed Resistance kz 5.3 Substrate (33 x 33 x 1.2 mm) kx ky kz 13.5 13.5 5.3 W/(m * K) W/(m * K)
Substrate
C5 Solder layer (33 x 33 x 0.4 mm) kx ky kz 0.034 0.034 9.6 y W/(m * K)
Die
Top View of Model (Not to Scale)
Figure 62. Recommended Thermal Model of MPC8640
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 119
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19.2.4
Temperature Diode
The MPC8640 has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as Analog Devices, ADT7461TM). These devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment. For proper operation, the monitoring device used should auto-calibrate the device by canceling out the VBE variation of each MPC8640's internal diode. The following are the specifications of the MPC8640 on-board temperature diode: Vf > 0.40 V Vf < 0.90 V Operating range 2-300 A Diode leakage < 10 nA @ 125C Ideality factor over 5-150 A at 60C: n = 1.0275 0.9% Ideality factor is defined as the deviation from the ideal diode equation: qVf ___
Ifw = Is e nKT - 1
Another useful equation is:
H VH - VL = n __ ln __
KT q
I IL
Where: Ifw = Forward current Is = Saturation current Vd = Voltage at diode Vf = Voltage forward biased VH = Diode voltage while IH is flowing VL = Diode voltage while IL is flowing IH = Larger diode bias current IL = Smaller diode bias current q = Charge of electron (1.6 x 10 -19 C) n = Ideality factor (normally 1.0) K = Boltzman's constant (1.38 x 10-23 Joules/K) T = Temperature (Kelvins)
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 120 Freescale Semiconductor
System Design Information
The ratio of IH to IL is usually selected to be 10:1. The above simplifies to the following:
VH - VL = 1.986 x 10-4 x nT
Solving for T, the equation becomes:
nT = VH - VL __________ 1.986 x 10-4
20 System Design Information
This section provides electrical and thermal design recommendations for successful application of the MPC8640.
20.1
System Clocking
This device includes six PLLs, as follows: 1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in Section 18.2, "MPX to SYSCLK PLL Ratio." 2. The dual e600 Core PLLs generate the e600 clock from the externally supplied input. 3. The local bus PLL generates the clock for the local bus. 4. There are two internal PLLs for the SerDes block.
20.2
20.2.1
Power Supply Design and Sequencing
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent filter circuits per PLL power supply as illustrated in Figure 64, one to each of the AVDD type pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. Each circuit should be placed as close as possible to the specific AVDD type pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD type pin, which is on the periphery of the footprint, without the inductance of vias.
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Figure 63 and Figure 64 show the PLL power supply filter circuits for the platform and cores, respectively.
VDD_PLAT 10 2.2 F 2.2 F Low ESL Surface Mount Capacitors GND AVDD_PLAT, AVDD_LB;
Figure 63. MPC8640 PLL Power Supply Filter Circuit (for platform and Local Bus)
Filter Circuit (should not be used for Single core device)
10 VDD_Core0/1 2.2 F 2.2 F Low ESL Surface Mount Capacitors AVDD_Core0/1
GND
Note: For single core device the filter circuit (in the dashed box) should be removed and AVDD_Core1 should be tied to ground with a weak (2-10 k) pull-down resistor.
Figure 64. MPC8640 PLL Power Supply Filter Circuit (for cores)
The AVDD_SRDSn signals provide power for the analog portions of the SerDes PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be near the AVDD_SRDSn balls. The 0.003-F capacitor is closest to the balls, followed by the two 2.2-F capacitors, and finally the 1 resistor to the board supply plane. The capacitors are connected from AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide and direct.
SVDD 1.0 AVDD_SRDSn 2.2 F
1
2.2 F
1
0.003 F
GND
1. An 0805 sized capacitor is recommended for system initial bring-up.
Figure 65. SerDes PLL Power Supply Filter
Note the following: * AVDD_SRDSn should be a filtered version of SVDD. * Signals on the SerDes interface are fed from the SVDD power plan.
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20.2.2
PLL Power Supply Sequencing
For details on power sequencing for the AVDD type and supplies refer to Section 2.2, "Power Up/Down Sequence."
20.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8640 system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren, and VDD_PLAT pin of the device. These decoupling capacitors should receive their power from separate OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren, and VDD_PLAT and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren, and VDD_PLAT planes, to enable quick recharging of the smaller chip capacitors. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors--100-330 F (AVX TPS tantalum or Sanyo OSCON).
20.4
SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD_SRDSn) to ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. * First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible. * Second, there should be a 1-F ceramic chip capacitor on each side of the device. This should be done for all SerDes supplies. * Third, between the device and any SerDes voltage regulator there should be a 10-F, low equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-F, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 123
System Design Information
20.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. In general all unused active low inputs should be tied to OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren, and VDD_PLAT, XVDD_SRDSn, and SVDD as required and unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Special cases: DDR - If one of the DDR ports is not being used the power supply pins for that port can be connected to ground so that there is no need to connect the individual unused inputs of that port to ground. Note that these power supplies can only be powered up again at reset for functionality to occur on the DDR port. Power supplies for other functional buses should remain powered. Local Bus - If parity is not used, tie LDP[0:3] to ground via a 4.7 k resistor, tie LPBSE to OVDD via a 4.7 k resistor (pull-up resistor). For systems which boot from Local Bus (GPCM)-controlled flash, a pullup on LGPL4 is required. SerDes - Receiver lanes configured for PCI Express are allowed to be disconnected (as would occur when a PCI Express slot is connected but not populated). Directions for terminating the SerDes signals is discussed in Section 20.5.1, "Guidelines for High-Speed Interface Termination."
20.5.1
20.5.1.1
Guidelines for High-Speed Interface Termination
SerDes Interface
The high-speed SerDes interface can be disabled through the POR input cfg_io_ports[0:3] and through the DEVDISR register in software. If a SerDes port is disabled through the POR input the user can not enable it through the DEVDISR register in software. However, if a SerDes port is enabled through the POR input the user can disable it through the DEVDISR register in software. Disabling a SerDes port through software should be done on a temporary basis. Power is always required for the SerDes interface, even if the port is disabled through either mechanism. Table 71 describes the possible enabled/disabled scenarios for a SerDes port. The termination recommendations must be followed for each port.
Table 71. SerDes Port Enabled/Disabled Configurations
Disabled through POR input SerDes port is disabled (and cannot be enabled through DEVDISR) Enabled through DEVDISR Complete termination required (Reference Clock not required) SerDes port is disabled (through POR input) Disabled through DEVDISR Complete termination required (Reference Clock not required) Enabled through POR input SerDes port is enabled Partial termination may be required 1 (Reference Clock is required) SerDes port is disabled after software disables port Same termination requirements as when the port is enabled through POR input 2 (Reference Clock is required)
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 124 Freescale Semiconductor
System Design Information
1
Partial Termination when a SerDes port is enabled through both POR input and DEVDISR is determined by the SerDes port mode. If the port is in x8 PCI Express mode, no termination is required because all pins are being used. If the port is in x1/x2/x4 PCI Express mode, termination is required on the unused pins. If the port is in x4 Serial RapidIO mode termination is required on the unused pins. 2 If a SerDes port is enabled through the POR input and then disabled through DEVDISR, no hardware changes are required. Termination of the SerDes port should follow what is required when the port is enabled through both POR input and DEVDISR. See Note 1 for more information.
If the high-speed SerDes port requires complete or partial termination, the unused pins should be terminated as described in this section. The following pins must be left unconnected (floating): * SDn_TX[7:0] * SDn_TX[7:0] The following pins must be connected to GND: * SDn_RX[7:0] * SDn_RX[7:0] * SDn_REF_CLK * SDn_REF_CLK
NOTE
It is recommended to power down the unused lane through SRDS1CR1[0:7] register (offset = 0xE_0F08) and SRDS2CR1[0:7] register (offset = 0xE_0F44.) (This prevents the oscillations and holds the receiver output in a fixed state.) that maps to SERDES lane 0 to lane 7 accordingly. For other directions on reserved or no-connects pins see Section 17, "Signal Listings."
20.6
Pull-Up and Pull-Down Resistor Requirements
The MPC8640 requires weak pull-up resistors (2-10 k is recommended) on all open drain type pins. The following pins must NOT be pulled down during power-on reset: TSEC4_TXD[4], LGPL0/LSDA10, LGPL1/LSDWE, TRIG_OUT/READY, and D1_MSRCID[2]. The following are factory test pins and require strong pull up resistors (100 -1 k) to OVDD LSSD_MODE, TEST_MODE[0:3].The following pins require weak pull up resistors (2-10 k) to their specific power supplies: LCS[0:4], LCS[5]/DMA_DREQ2, LCS[6]/DMA_DACK[2], LCS[7]/DMA_DDONE[2], IRQ_OUT, IIC1_SDA, IIC1_SCL, IIC2_SDA, IIC2_SCL, and CKSTP_OUT. The following pins should be pulled to ground with a 100- resistor: SD1_IMP_CAL_TX, SD2_IMP_CAL_TX. The following pins should be pulled to ground with a 200- resistor: SD1_IMP_CAL_RX, SD2_IMP_CAL_RX. TSECn_TX_EN signals require an external 4.7-k pull down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. When the platform frequency is 400 MHz, TSEC1_TXD[1] must be pulled down at reset.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 125
System Design Information
TSEC2_TXD[4] and TSEC2_TX_ER pins function as cfg_dram_type[0 or 1] at reset and MUST BE VALID BEFORE HRESET ASSERTION when coming out of device sleep mode.
20.6.1
Special instructions for Single Core device
The mechanical drawing for the single core device does not have all the solder balls that exist on the single core device. This includes all the balls for VDD_Core1 and SENSEVDD_Core1 which exist on the package for the dual core device, but not on the single core package. A solder ball is present for SENSEVSS_Core1 and needs to be connected to ground with a weak (2-10 k) pull down resistor. Likewise, AVDD_Core1 needs to be pulled to ground as shown in Figure 64. The mechanical drawing for the single core device is located in Section 16.2, "Mechanical Dimensions of the MPC8640 FC-CBGA." For other pin pull-up or pull-down recommendations of signals, please see Section 17, "Signal Listings."
20.7
Output Buffer DC Impedance
The MPC8640 drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 66). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
OV DD
RN
SW2 Data Pad SW1
RP
OGND
Figure 66. Driver Impedance Measurement
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 126 Freescale Semiconductor
System Design Information
Table 72 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD, nominal OVDD, 105C.
Table 72. Impedance Characteristics
Impedance RN RP DUART, Control, Configuration, Power Management 43 Target 43 Target PCI Express 25 Target 25 Target DDR DRAM 20 Target 20 Target Symbol Z0 Z0 Unit W W
Note: Nominal supply voltages. See Table 1, Tj = 105C.
20.8
Configuration Pin Muxing
The MPC8640 provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k. This value should permit the 4.7-k resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage level puts the device into the default state and external resistors are needed only when non-default settings are required by the user. Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. The platform PLL ratio and e600 PLL ratio configuration pins are not equipped with these default pull-up devices.
20.9
JTAG Configuration Signals
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 68. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the Power Architecture technology. The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 127
System Design Information
if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP port connects primarily through the JTAG interface of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 67 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. The COP interface has a standard header, shown in Figure 67, for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed. There is no standardized way to number the COP header shown in Figure 67; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 67 is common to all known emulators. For a multi-processor non-daisy chain configuration, Figure 68, can be duplicated for each processor. The recommended daisy chain configuration is shown in Figure 69. Please consult with your tool vendor to determine which configuration is supported by their emulator.
20.9.1 Termination of Unused Signals
If the JTAG interface and COP header will not be used, Freescale recommends the following connections: * TRST should be tied to HRESET through a 0 k isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in Figure 68. If this is not possible, the isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations. * Tie TCK to OVDD through a 10 k resistor. This will prevent TCK from changing state and reading incorrect data into the device. * No connection is required for TDI, TMS, or TDO.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 128 Freescale Semiconductor
System Design Information
COP_TDO COP_TDI NC COP_TCK COP_TMS COP_SRESET COP_HRESET COP_CHKSTP_OUT
1 3 5 7 9 11 13 15
2 4 6 8 10 12 KEY No pin 16
NC COP_TRST COP_VDD_SENSE COP_CHKSTP_IN NC NC
GND
Figure 67. COP Connector Physical Pinout
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 129
System Design Information
OVDD
SRESET0 From Target Board Sources (if any)
10 k
SRESET0
SRESET1 HRESET 13 11 COP_HRESET COP_SRESET
10 k
SRESET1 HRESET1
10 k
10 k 10 k
5
10 k 10 k TRST1
1 3 5 7 9 11
2 4 6 8 10 12
4 6 COP Header 5 15 14 3
COP_TRST COP_VDD_SENSE2 NC COP_CHKSTP_OUT 10 k 10 k COP_CHKSTP_IN 10
CKSTP_OUT
KEY 13 No pin
8 COP_TMS 9 COP_TDO COP_TDI COP_TCK 7 2 10 12 16 NC NC
4
CKSTP_IN TMS TDO TDI TCK 10 k
15
16
COP Connector Physical Pinout
1 3
Notes: 1. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown here. 2. Populate this with a 10 resistor for short-circuit/current-limiting protection. 3. The KEY location (pin 14) is not physically present on the COP header. 4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity. 5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.
Figure 68. JTAG/COP Interface Connection for one MPC8640 device
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 130 Freescale Semiconductor
Ordering Information
OVDD
10k 10k SRESET0 From Target Board Sources (if any) SRESET1 HRESET
10k TDI MPC8640 SRESET0 SRESET1 3 OVDD 10k HRESET 4 TRST 4 CHKSTP_OUT CHKSTP_IN TMS TCK TDO
3 COP_TDI COP_SRESET COP_HRESET 10k 11 13
10k 10k 10k
10k 10k
5
3 NC
4 COP_TRST 5 15 8 2 10 2 COP_TMS COP_TCK GND 14 9 7 12 16
COP_CHKSTP_OUT COP_CHKSTP_IN JTAG/COP Header
NC NC
TDI MPC8640 SRESET0 SRESET1 HRESET 4 TRST 4
6 10
1 6 COP_VDD_SENSE COP_TDO 1 Notes:
CHKSTP_OUT CHKSTP_IN TMS TCK TDO
1. Populate this with a 10 resistor for short circuit/current-limiting protection. 2. KEY location; pin 14 is not physically present on the COP header. 3. Use a AND gate with sufficient drive strength to drive two inputs. 4. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown above. 5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed. 6. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity.
Figure 69. JTAG/COP Interface Connection for Multiple MPC8640 Devices in Daisy Chain Configuration
21 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section 21.1, "Part Numbers Fully Addressed by This Document."
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 131
Ordering Information
21.1
Part Numbers Fully Addressed by This Document
Table 73 provides the Freescale part numbering nomenclature for the MPC8640. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number.
Table 73. Part Numbering Nomenclature
uu nnnn D w xx yyyy Core Processor Frequency 2 (MHz) a z
Product Part Code Identifier
Core Count
Temp
Package
1
DDR speed (MHz)
Product Revision Level
Blank = Single Core MC5 8640 D= Dual Core
Revision C = 2.1 System Version Register Value for Rev C: 4 1000, 1067, N = 533 MHz 0x8090_0021 - MPC8640 1250 T: VU = RoHS lead-f H = 500 MHz 0x8090_0121 - MPC8640D -40C to 105C ree HCTE FC-CBGA Blank: 0C to 105C HX = High-lead HCTE FC-CBGA
Notes: 1. See Section 16, "Package," for more information on available package types. 2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by part number specifications may support other maximum core frequencies. 3. The P prefix in a Freescale part number designates a "Pilot Production Prototype" as defined by Freescale SOP 3-13. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes. 4. Part Number MC8640xxx1067NC is our low VDD_Coren device. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V. 5. MC - Qualified production
Table 74 shows the parts that are available for ordering and their operating conditions.
Table 74. Part Offerings and Operating Conditions
Part Offerings 1 MC8640Dwxx1250HC Operating Conditions Dual core Max CPU speed = 1250 MHz, Max DDR = 500 MHz Core Voltage = 1.05 volts Dual core Max CPU speed = 1000 MHz, Max DDR = 500 MHz Core Voltage = 1.05 volts
MC8640Dwxx1000HC
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 132 Freescale Semiconductor
Ordering Information
Table 74. Part Offerings and Operating Conditions
Part Offerings 1 MC8640Dwxx1067NC Operating Conditions Dual core MAX CPU speed = 1067 MHz, MAX DDR = 533 MHz Core Voltage = 0.95 volts Single core Max CPU speed = 1250 MHz, Max DDR = 500 MHz Core Voltage = 1.05 volts Single core Max CPU speed = 1000 MHz, Max DDR = 500 MHz Core Voltage = 1.05 volts Single core Max CPU speed = 1067 MHz, Max DDR = 533 MHz Core Voltage = 0.95 volts
MC8640wxx1250HC
MC8640wxx1000HC
MC8640wxx1067NC
1
Note that the "w" represents the operating temperature range. The "xx" in the part marking represents the package option. For more information see Table 73.
21.2
Part Marking
Parts are marked as the example shown in Figure 70.
MC8640x xxnnnnxx
TWLYYWW MMMMMM YWWLAZ 8640D
NOTE: TWLYYWW is the test code MMMMMM is the M00 (mask) number. YWWLAZ is the assembly traceability code.
Figure 70. Part Marking for FC-CBGA Device
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 133
Ordering Information
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 134 Freescale Semiconductor
Document Revision History
22 Document Revision History
Table 76 provides a revision history for the MPC8640D hardware specification.
Table 75. Document Revision History
Revision 1 Date 11/2008 Substantive Change(s) * Removed voltage option of 1.10 V from Table 2 because it is not supported by MPC8640D or MPC8640 * Updated Table 4 and Table 5 with the new 1067/533 MHz device offering. This includes updated Power Specifications. * Added Section 4.4, "Platform Frequency Requirements for PCI-Express and Serial RapidIO" * Updated Section 6, "DDR and DDR2 SDRAM" to include 533 MHz. * Added core frequency of 1067 to Table 63, Table 64, Table 65 and Table 66 * Changed Max Memory clock frequency from 250 MHz to 266 MHz in Table 64 * Changed Max MPX/Platform clock Frequency from 500 MHz to 533 MHz in Table 65 * Changed Max Local Bus clock speed from 1 MHz to 133 MHz in Table 66 * Added MPX:Sysclk Ratio of 8:1 to Table 67 * Added Core:MPX Ratio of 3:1 to Table 68 * Updated Table 69 to include 533 MPX clock frequency * Changed the Extended Temp range part numbering `w' to be T instead of an H in Table 73 * Changed the DDR speed part numbering N to stand for 533 MHz intead of 500 MHz in Table 73 * Removed the statement "Note that core processor speed of 1500 MHz is only available for the MPC8640D (dual core)" from Note 2 in Table 73 because MPC8640D is not offered at 1500 MHz core. * Removed the part offering MC8640Dwxx1000NC which is replaced with MC8640Dwxx1067NC and removed MC8640wxx1000NC replaced with MC8640wxx1067NC in Table 74 * Added Note 8 to Figure 57 and Figure 58. * Initial Release
0
07/2008
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Document Number: MPC8640DEC Rev. 1 11/2008

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